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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. x87 floating-point exception pending, #MF X X X An exception was pending due to an x87 floating-point instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. 56 CVTPI2PD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTPI2PS Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Converts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location to two single-precision floating-point values and writes the converted values in the low-order 64 bits of an XMM register. The high-order 64 bits of the XMM register are not modified. Mnemonic Opcode Description CVTPI2PS xmm, mmx/mem64 0F 2A /r Converts packed doubleword integer values in an MMX register or 64-bit memory location to single-precision floating-point values in the destination XMM register. xmm mmx/mem64 127 64 63 32 31 0 63 32 31 0 convert convert cvtpi2ps.eps Related Instructions CVTDQ2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI, CVTTSS2SI rFLAGS Affected None CVTPI2PS 57
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