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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MINPD Minimum Packed Double-Precision Floating- Point Compares each of the two packed double-precision floating-point values in the first source operand with the corresponding packed double-precision floating-point value in the second source operand and writes the numerically lesser of the two values for each comparison in the corresponding quadword of the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or a 128-bit memory location. Mnemonic Opcode Description MINPD xmm1, xmm2/mem128 66 0F 5D /r Compares two pairs of packed double-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and writes the lesser value of each comparison in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 64 63 0 minimum minimum minpd.eps If both source operands are equal to zero, the value in the second source operand is returned. If either operand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second source operand is written to the destination. Related Instructions MAXPD, MAXPS, MAXSD, MAXSS, MINPS, MINSD, MINSS rFLAGS Affected None 130 MINPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. SIMD Floating-Point Exception, #XF Invalid-operation exception (IE) Denormalized-operand exception (DE) X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions X X X A source operand was an SNaN or QNaN value. X X X A source operand was a denormal value. MINPD 131
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