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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 PSHUFD Packed Shuffle Doublewords Moves any one of the four packed doublewords in an XMM register or 128-bit memory location to each doubleword in another XMM register. In each case, the value of the destination doubleword is determined by a two-bit field in the immediate-byte operand, with bits 0 and 1 selecting the contents of the low-order doubleword, bits 2 and 3 selecting the second doubleword, bits 4 and 5 selecting the third doubleword, and bits 6 and 7 selecting the high-order doubleword. Refer to Table 1-4 on page 277. A doubleword in the source operand may be copied to more than one doubleword in the destination. Mnemonic Opcode Description PSHUFD xmm1, xmm2/mem128, imm8 66 0F 70 /r ib Moves packed 32-bit values in an XMM register or 128-bit memory location to doubleword locations in another XMM register, as selected by the immediate-byte operand. xmm1 xmm2/mem128 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 imm8 7 0 mux mux mux mux pshufd.eps 276 PSHUFD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology Table 1-4. Immediate-Byte Operand Encoding for PSHUFD Destination Bits Filled Immediate-Byte Bit Field Value of Bit Field Source Bits Moved 0 31–0 31–0 1–0 1 63–32 2 95–64 3 127–96 0 31–0 63–32 3–2 1 63–32 2 95–64 3 127–96 0 31–0 95–64 5–4 1 63–32 2 95–64 3 127–96 0 31–0 127–96 7–6 1 63–32 2 95–64 3 127–96 Related Instructions PSHUFHW, PSHUFLW, PSHUFW rFLAGS Affected None MXCSR Flags Affected None PSHUFD 277
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