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<strong>AMD</strong> <strong>64</strong>-<strong>Bit</strong> <strong>Technology</strong> 26568—Rev. 3.02—August 2002<br />

MASKMOVDQU implicitly uses weakly-ordered, write-combining buffering for the<br />

data, as described in “Buffering and Combining Memory Writes” in Volume 2. For<br />

data that is shared by multiple processors, this instruction should be used together<br />

with a fence instruction in order to ensure data coherency (refer to “Cache and TLB<br />

Management” in Volume 2).<br />

Related Instructions<br />

MASKMOVQ<br />

rFLAGS Affected<br />

None<br />

MXCSR Flags Affected<br />

None<br />

Exceptions<br />

Exception<br />

Invalid opcode, #UD<br />

Real<br />

X<br />

Virtual<br />

8086 Protected Cause of Exception<br />

X<br />

X<br />

The SSE2 instructions are not supported, as indicated by bit<br />

26 of CPUID standard function 1.<br />

X<br />

X<br />

X<br />

The emulate bit (EM) of CR0 was set to 1.<br />

X X X The operating-system FXSAVE/FXRSTOR support bit<br />

(OSFXSR) of CR4 is cleared to 0.<br />

Device not available, X X X The task-switch bit (TS) of CR0 was set to 1.<br />

#NM<br />

Stack, #SS X X X A memory address exceeded the stack segment limit or was<br />

non-canonical.<br />

General protection, #GP X X X<br />

A memory address exceeded a data segment limit or was<br />

non-canonical.<br />

X A null data segment was used to reference memory.<br />

Page fault, #PF X X A page fault resulted from the execution of the instruction.<br />

120 MASKMOVDQU

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