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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. Device not available, #NM X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. 154 MOVHLPS
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVHPD Move High Packed Double-Precision Floating-Point Moves a double-precision floating-point value: „ from a 64-bit memory location to the high-order 64 bits of an XMM register, or „ from the high-order 64 bits of an XMM register to a 64-bit memory location. The low-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVHPD xmm, mem64 66 0F 16 /r Moves double-precision floating-point value from a 64-bit memory location to an XMM register. MOVHPD mem64, xmm 66 0F 17 /r Moves double-precision floating-point value from an XMM register to a 64-bit memory location. xmm 127 64 63 0 mem64 63 0 copy mem64 63 0 xmm 127 32 31 0 copy movhpd.eps Related Instructions MOVAPD, MOVLPD, MOVMSKPD, MOVSD, MOVUPD rFLAGS Affected None MOVHPD 155
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