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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP Real X Virtual 8086 Protected Cause of Exception X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 352 SHUFPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology SHUFPS Shuffle Packed Single-Precision Floating-Point Moves two of the four packed single-precision floating-point values in the first source operand to the low-order quadword of the destination (first source) and moves two of the four packed single-precision floating-point values in the second source operand to the high-order quadword of the destination. In each case, the value of the destination doubleword is determined by a two-bit field in the immediate-byte operand, as shown in Table 1-8 on page 354. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description SHUFPS xmm1, xmm2/mem128, imm8 0F C6 /r ib Shuffles packed single-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and puts the result in the destination XMM register. xmm1 xmm2/mem128 127 64 63 0 127 96 95 64 63 32 31 0 imm8 7 0 mux mux shufps.eps SHUFPS 353
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