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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. 388 UNPCKHPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology UNPCKHPS Unpack High Single-Precision Floating-Point Unpacks the high-order single-precision floating-point values in the first and second source operands and packs them into interleaved doublewords in the destination (first source). The low-order quadwords of the source operands are ignored. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description UNPCKHPS xmm1, xmm2/mem128 0F 15 /r Unpacks high-order single-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and packs them into the destination XMM register. xmm1 xmm2/mem128 127 96 95 64 63 0 127 96 95 64 63 0 copy copy copy copy 127 96 95 64 63 32 31 0 unpckhps.eps Related Instructions UNPCKHPD, UNPCKLPD, UNPCKLPS rFLAGS Affected None MXCSR Flags Affected None UNPCKHPS 389
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