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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Exception Invalid-operation exception (IE) Real X Virtual 8086 Protected Cause of Exception X SIMD Floating-Point Exceptions X A source operand was an SNaN value, a QNaN value, or ±infinity. X X X A source operand was too large to fit in the destination format. Precision exception (PE) X X X A result could not be represented exactly in the destination format. 66 CVTPS2PI
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology CVTSD2SI Convert Scalar Double-Precision Floating-Point to Signed Doubleword or Quadword Integer Converts a scalar double-precision floating-point value in the low-order 64 bits of an XMM register or a 64-bit memory location to a 32-bit or 64-bit signed integer and writes the converted value in a general-purpose register. Mnemonic Opcode Description CVTSD2SI reg32, xmm/mem64 F2 0F 2D /r Converts a packed double-precision floating-point value in an XMM register or 64-bit memory location to a doubleword integer in a general-purpose register. CVTSD2SI reg64, xmm/mem64 F2 0F 2D /r Converts a packed double-precision floating-point value in an XMM register or 64-bit memory location to a quadword integer in a general-purpose register. reg32 xmm2/mem64 31 0 127 64 63 0 convert reg64 xmm2/mem64 63 0 127 64 63 0 convert with REX prefix cvtsd2si.eps If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1) or quadword value (–2 63 to +2 63 – 1), the instruction returns the indefinite integer value (8000_0000h for 32-bit integers, CVTSD2SI 67
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