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26568—Rev. 3.02—August 2002
AMD 64-Bit Technology
MINSS
Minimum Scalar Single-Precision Floating-Point
Compares the single-precision floating-point value in the low-order 32 bits of the first
source operand with the single-precision floating-point value in the low-order 32 bits
of the second source operand and writes the numerically lesser of the two values in
the low-order 32 bits of the destination (first source). The first source/destination
operand is an XMM register. The second source operand is another XMM register or a
32-bit memory location. The three high-order doublewords of the destination XMM
register are not modified.
Mnemonic Opcode Description
MINSS xmm1, xmm2/mem32 F3 0F 5D /r Compares scalar single-precision floating-point values in an XMM
register and another XMM register or 32-bit memory location and
writes the lesser of the two values in the destination XMM register.
xmm1
xmm2/mem32
127 32 31 0 127 32 31 0
minimum
minss.eps
If both source operands are equal to zero, the value in the second source operand is
returned. If either operand is a NaN (SNaN or QNaN), and invalid-operation
exceptions are masked, the second source operand is written to the destination.
Related Instructions
MAXPD, MAXPS, MAXSD, MAXSS, MINPD, MINPS, MINSD
rFLAGS Affected
None
MINSS 137