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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. 156 MOVHPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVHPS Move High Packed Single-Precision Floating-Point Moves two packed single-precision floating-point values: „ from a 64-bit memory location to the high-order 64 bits of an XMM register, or „ from the high-order 64 bits of an XMM register to a 64-bit memory location. The low-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVHPS xmm, mem64 0F 16 /r Moves two packed single-precision floating-point values from a 64-bit memory location to an XMM register. MOVHPS mem64, xmm 0F 17 /r Moves two packed single-precision floating-point values from an XMM register to a 64-bit memory location. xmm mem64 127 96 95 64 63 0 63 32 31 0 copy copy mem64 xmm 63 32 31 0 127 96 95 64 63 0 copy copy movhps.eps Related Instructions MOVAPS, MOVHLPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPS MOVHPS 157
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