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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. 176 MOVQ
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVQ2DQ Move Quadword to Quadword Moves a 64-bit value from an MMX register to the low-order 64 bits of an XMM register, with zero-extension to 128 bits. Mnemonic Opcode Description MOVQ2DQ xmm, mmx F3 0F D6 /r Moves 64-bit value from an MMX register to an XMM register. 127 64 63 0 0 xmm mmx 63 0 copy movq2dq.eps Related Instructions MOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ rFLAGS Affected None MXCSR Flags Affected None MOVQ2DQ 177
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