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AMD 64-Bit Technology 26568—Rev. 3.02—August 2002 Related Instructions MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Invalid opcode, #UD Real X Virtual 8086 Protected Cause of Exception X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. X X X The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, X X X The task-switch bit (TS) of CR0 was set to 1. #NM Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned-memory reference was performed while alignment checking was enabled. 186 MOVUPD
26568—Rev. 3.02—August 2002 AMD 64-Bit Technology MOVUPS Move Unaligned Packed Single-Precision Floating-Point Moves four packed single-precision floating-point values: „ from an XMM register or 128-bit memory location to another XMM register, or „ from an XMM register to another XMM register or 128-bit memory location. Mnemonic Opcode Description MOVUPS xmm1, xmm2/mem128 0F 10 /r Moves four packed single-precision floating-point values from an XMM register or unaligned 128-bit memory location to an XMM register. MOVUPS xmm1/mem128, xmm2 0F 11 /r Moves four packed single-precision floating-point values from an XMM register to an XMM register or unaligned 128-bit memory location. xmm1 xmm2/mem128 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 copy copy copy copy xmm1/mem128 xmm2 127 96 95 64 63 32 31 0 127 96 95 64 63 32 31 0 copy copy copy copy movups.eps MOVUPS 187
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