ModelSim SE User's Manual - Electrical and Computer Engineering

UM-108 4 - VHDL simulation
Affecting performance by cancelling scheduled events
ModelSim SE User’s Manual
Performance will suffer if events are scheduled far into the future but then cancelled before
they take effect. This situation will act like a memory leak and slow down simulation.
In VHDL this situation can occur several ways. The most common are waits with time-out
clauses and projected waveforms in signal assignments.
The following code shows a wait with a time-out:
signals synch : bit := '0';
...
p: process
begin
wait for 10 ms until synch = 1;
end process;
synch