ModelSim SE User's Manual - Electrical and Computer Engineering

Simulator resolution limit
Runtime modeling semantics
Separate compilers, common design libraries UM-191
In a mixed-language design with only one top, the resolution of the top design unit is
applied to the whole design. If the root of the mixed design is VHDL, then VHDL simulator
resolution rules are used (see "Simulator resolution limit" (UM-78) for VHDL details). If the
root of the mixed design is Verilog, Verilog rules are used (see "Simulator resolution limit"
(UM-129) for Verilog details). If the root is SystemC, then SystemC rules are used (see
"Running simulation" (UM-173) for SystemC details).
In the case of a mixed-language design with multiple tops, the following algorithm is used:
If VHDL or SystemC modules are present, then the Verilog resolution is ignored. An
error is issued if the Verilog resolution is finer than the chosen one.
If both VHDL and SystemC are present, then the resolution is chosen based on which
design unit is elaborated first. For example:
vsim sc_top vhdl_top -do vsim.do
In this case the SystemC resolution will be chosen.
vsim vhdl_top sc_top -do vsim.do
In this case the VHDL resolution will be chosen.
All resolutions specified in the source files are ignored if vsim is invoked with the -t
option.
The ModelSim simulator is compliant with all pertinent Language Reference Manuals. To
achieve this compliance, the sequence of operations in one simulation iteration (i.e. delta
cycle) is as follows:
SystemC processes are run
Signal updates are made
HDL processes are run
ModelSim SE User’s Manual