ModelSim SE User's Manual - Electrical and Computer Engineering

Related tasks
Limitations
Example
Name Type Description
$init_signal_driver (UM-429), $signal_force (UM-434), $signal_release (UM-436)
When mirroring the value of a VHDL signal onto a Verilog register, the VHDL signal
must be of type bit, bit_vector, std_logic, or std_logic_vector.
Verilog memories (arrays of registers) are not supported.
module top;
...
reg top_sig1;
reg enable_reg;
...
initial
begin
$init_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",1,1);
end
always @ (posedge enable_reg)
begin
$enable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0);
end
always @ (negedge enable_reg)
begin
$disable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0);
end
...
endmodule
In this example, the value of .top.uut.inst1.sig1 is mirrored onto .top.top_sig1.
$init_signal_spy UM-433
dest_object string Required. A full hierarchical path (or relative
path with reference to the calling block) to a
Verilog register or VHDL signal. Use the path
separator to which your simulation is set (i.e.,
"/" or "."). A full hierarchical path must begin
with a "/" or ".". The path must be contained
within double quotes.
verbose integer Optional. Possible values are 0 or 1. Specifies
whether you want a message reported in the
Transcript stating that the src_object’s value
is mirrored onto the dest_object. Default is 0,
no message.
ModelSim SE User’s Manual