ModelSim SE User's Manual - Electrical and Computer Engineering

UM-432 17 - Signal Spy
$init_signal_spy
Call only once
Syntax
Returns
Arguments
ModelSim SE User’s Manual
The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog register/
net (called the src_object) onto an existing VHDL signal or Verilog register (called the
dest_object). This allows you to reference signals, registers, or nets at any level of hierarchy
from within a Verilog module (e.g., a testbench).
The $init_signal_spy system task only sets the value onto the destination signal and does
not drive or force the value. Any existing or subsequent drive or force of the destination
signal, by some other means, will override the value set by $init_signal_spy.
The $init_signal_spy system task creates a persistent relationship between the source and
the destination signal. Hence, you need to call $init_signal_spy only once for a particular
pair of signals. Once $init_signal_spy is called, any change on the source signal will mirror
on the destination signal until the end of the simulation.
We recommend that you place all $init_signal_spy tasks in a Verilog initial block. See the
example below.
Nothing
$init_signal_spy(src_object, dest_object, verbose)
Name Type Description
src_object string Required. A full hierarchical path (or relative
path with reference to the calling block) to a
VHDL signal or Verilog register/net. Use the
path separator to which your simulation is set
(i.e., "/" or "."). A full hierarchical path must
begin with a "/" or ".". The path must be
contained within double quotes.