ModelSim SE User's Manual - Electrical and Computer Engineering

UM-210 7 - Mixed-language simulation
ModelSim SE User’s Manual
Guidelines for manual creation
Apply the following guidelines to the creation of foreign modules. A foreign module:
contains ports corresponding to Verilog ports. These ports must be explicitly named in
the foreign module’s constructor initializer list.
must not contain any internal design elemen ts such as child instances, primitive channels,
or processes.
must pass a secondary constructor argument denoting the module’s HDL name to the
sc_foreign_module base class constructor. For Verilog, the HDL name is simply the
Verilog module name corresponding to the foreign module, or []..
parameterized modules are allowed, see "Parameter support for SystemC instantiating
Verilog" (UM-211) for details.
Example #1
A sample Verilog module to be instantiated in a SystemC design is:
module vcounter (clock, topcount, count);
input clock;
input topcount;
output count;
reg count;
...
endmodule
The SystemC foreign module declaration for the above Verilog module is:
class counter : public sc_foreign_module {
public:
sc_in clock;
sc_in topcount;
sc_out count;
counter(sc_module_name nm)
: sc_foreign_module(nm, "lib.vcounter"),
clock("clock"),
topcount("topcount"),
count("count")
{}
};
The Verilog module is then instantiated in the SystemC source as follows:
counter dut("dut");
where the constructor argument (dut) is the instance name of the Verilog module.