ModelSim SE User's Manual - Electrical and Computer Engineering

Related tasks
Limitations
Example
Name Type Description
cancel_period integer, real, time Optional. Cancels the $signal_force command
after the specified period of time units.
Cancellation occurs at the last simulation
delta cycle of a time unit. A value of zero
cancels the force at the end of the current time
period. Default is -1. A negative value means
that the force will not be cancelled.
verbose integer Optional. Possible values are 0 or 1. Specifies
whether you want a message reported in the
Transcript stating that the value is being
forced on the dest_object at the specified time.
Default is 0, no message.
$init_signal_driver (UM-429), $init_signal_spy (UM-432), $signal_release (UM-436)
You cannot force bits or slices of a register; you can force only the entire register.
Verilog memories (arrays of registers) are not supported.
`timescale 1 ns / 1 ns
module testbench;
initial
begin
$signal_force("/testbench/uut/blk1/reset", "1", 0, 3, , 1);
$signal_force("/testbench/uut/blk1/reset", "0", 40, 3, 200000, 1);
end
...
endmodule
The above example forces reset to a "1" from time 0 ns to 40 ns. At 40 ns, reset is forced
to a "0", 200000 ns after the second $signal_force call was executed.
$signal_force UM-435
ModelSim SE User’s Manual