ModelSim SE User's Manual - Electrical and Computer Engineering

Mapping data types
Verilog to VHDL mappings
Mapping data types UM-193
Cross-language (HDL) instantiation does not require any extra effort on your part. As
ModelSim loads a design it detects cross-language instantiations – made possible because
a design unit's language type can be determined as it is loaded from a library – and the
necessary adaptations and data type conversions are performed automatically. SystemC
and HDL cross-language instantiation requires minor modification of SystemC source code
(addition of SC_MODULE_EXPORT, sc_foreign_module, etc.).
A VHDL instantiation of Verilog may associate VHDL signals and values with Verilog
ports and parameters. Likewise, a Verilog instantiation of VHDL may associate Verilog
nets and values with VHDL ports and generics. The same holds true for SystemC and
VHDL/Verilog ports.
ModelSim automatically maps between the language data types as shown in the sections
below.
Verilog parameters
Verilog type VHDL type
integer integer
real real
string string
The type of a Verilog parameter is determined by its initial value.
Verilog ports
The allowed VHDL types for ports connected to Verilog nets and for signals connected to
Verilog ports are:
Allowed VHDL types
bit
bit_vector
std_logic
std_logic_vector
vl_logic
vl_logic_vector
The vl_logic type is an enumeration that defines the full state set for Verilog nets, including
ambiguous strengths. The bit and std_logic types are convenient for most applications, but
the vl_logic type is provided in case you need access to the full Verilog state set. For
ModelSim SE User’s Manual