ModelSim SE User's Manual - Electrical and Computer Engineering

UM-452 18 - Standard Delay Format (SDF) Timing Annotation
Troubleshooting
Specifying the wrong instance
ModelSim SE User’s Manual
By far, the most common mistake in SDF annotation is to specify the wrong instance to the
simulator’s SDF options. The most common case is to leave off the instance altogether,
which is the same as selecting the top-level design unit. This is generally wrong because
the instance paths in the SDF are relative to the ASIC or FPGA model, which is usually
instantiated under a top-level testbench. See "Instance specification" (UM-440) for an
example.
A common example for both VHDL and Verilog testbenches is provided below. For
simplicity, the test benches do nothing more than instantiate a model that has no ports.
VHDL testbench
entity testbench is end;
architecture only of testbench is
component myasic
end component;
begin
dut : myasic;
end;
Verilog testbench
module testbench;
myasic dut();
endmodule
The name of the model is myasic and the instance label is dut. For either testbench, an
appropriate simulator invocation might be:
vsim -sdfmax /testbench/dut=myasic.sdf testbench
Optionally, you can leave off the name of the top-level:
vsim -sdfmax /dut=myasic.sdf testbench
The important thing is to select the instance for which the SDF is intended. If the model is
deep within the design hierarchy, an easy way to find the instance name is to first invoke
the simulator without SDF options, view the structure pane, navigate to the model instance,
select it, and enter the environment command (CR-161). This command displays the
instance name that should be used in the SDF command-line option.