ModelSim SE User's Manual - Electrical and Computer Engineering

Creating foreign architectures with hm_entity
VHDL hardware model interface UM-629
The ModelSim hm_entity tool automatically creates entities and foreign architectures for
hardware models. Its usage is as follows:
Syntax
hm_entity
[-xe] [-xa] [-c] [-93]
Arguments
-xe
Do not generate entity declarations.
-xa
Do not generate architecture bodies.
-c
Generate component declarations.
-93
Use extended identifiers where needed.
Hardware model shell software filename (see Logic Modeling documentation from
Synopsys for details on shell software files)
By default, the hm_entity tool writes an entity and foreign architecture to stdout for the
hardware model. Optionally, you can include the component declaration (-c), exclude the
entity (-xe), and exclude the architecture (-xa).
Once you have created the entity and foreign architecture, you must compile it into a
library. For example, the following commands compile the entity and foreign architecture
for a hardware model named LMTEST:
% hm_entity LMTEST.MDL > lmtest.vhd
% vlib lmc
% vcom -work lmc lmtest.vhd
To instantiate the hardware model in your VHDL design, you will also need to generate a
component declaration. If you have multiple hardware models, you may want to add all of
their component declarations to a package so that you can easily reference them in your
design. The following command writes the component declaration to stdout for the
LMTEST hardware model.
% hm_entity -c -xe -xa LMTEST.MDL
Paste the resulting component declaration into the appropriate place in your design or into
a package.
The following is an example of the entity and foreign architecture created by hm_entity for
the CY7C285 hardware model:
library ieee;
use ieee.std_logic_1164.all;
entity cy7c285 is
generic ( DelayRange : STRING := "Max" );
port ( A0 : in std_logic;
ModelSim SE User’s Manual