ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-236 8 - WLF files (datasets) and virtuals ModelSim SE User’s Manual
9 - Waveform analysis Chapter contents Introduction . . . . . . . . . . . . . . . UM-239 Objects you can view . . . . . . . . . . . . UM-239 Wave window overview . . . . . . . . . . . . UM-240 List window overview . . . . . . . . . . . . . UM-240 Adding objects to the Wave or List window . . . . . . . UM-244 Measuring time with cursors in the Wave window . . . . . UM-245 Working with cursors . . . . . . . . . . . . UM-245 Understanding cursor behavior . . . . . . . . . UM-246 Jumping to a signal transition . . . . . . . . . . UM-247 Setting time markers in the List window . . . . . . . . UM-248 Working with markers . . . . . . . . . . . UM-248 Zooming the Wave window display . . . . . . . . . UM-249 Saving zoom range and scroll position with bookmarks . . . UM-250 Searching in the Wave and List windows . . . . . . . . UM-251 Finding signal names . . . . . . . . . . . . UM-251 Searching for values or transitions . . . . . . . . UM-252 Using the Expression Builder for expression searches . . . UM-253 Formatting the Wave window . . . . . . . . . . . UM-255 Setting Wave window display properties . . . . . . . UM-255 Formatting objects in the Wave window . . . . . . . UM-255 Changing radix (base) . . . . . . . . . . . . UM-259 Dividing the Wave window . . . . . . . . . . UM-256 Splitting Wave window panes. . . . . . . . . . UM-257 Formatting the List window . . . . . . . . . . . UM-259 Setting List window display properties . . . . . . . UM-259 Formatting objects in the List window . . . . . . . UM-259 Saving the window format . . . . . . . . . . . . UM-261 Printing and saving waveforms in the Wave window . . . . . UM-262 Saving a .eps file and printing under UNIX . . . . . . UM-262 Printing on Windows platforms . . . . . . . . . UM-262 Printer page setup . . . . . . . . . . . . . UM-262 Saving List window data to a file . . . . . . . . . . UM-263 Combining objects/creating busses . . . . . . . . . UM-264 Example . . . . . . . . . . . . . . . UM-264 Configuring new line triggering in the List window . . . . . UM-265 Using gating expressions to control triggering . . . . . UM-266 Sampling signals at a clock change . . . . . . . . UM-268 UM-237 ModelSim SE User’s Manual
Page 1 and 2:
ModelSim® Advanced Verification an
Page 3 and 4:
Table of Contents 1 - Introduction
Page 5 and 6:
Delta delays . . . . . . . . . . .
Page 7 and 8:
ModelSim Verilog system tasks and f
Page 9 and 10:
VHDL: instantiating SystemC . . . .
Page 11 and 12:
Creating waveforms from patterns .
Page 13 and 14:
14 - PSL Assertions (UM-359) What a
Page 15 and 16:
17 - Signal Spy (UM-417) Introducti
Page 17 and 18:
Starting the debugger . . . . . . .
Page 19 and 20:
Steps in flow . . . . . . . . . . .
Page 21 and 22:
1 - Introduction Chapter contents M
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ModelSim simulation task overview M
Page 25 and 26:
Basic steps for simulation UM-25 Li
Page 27 and 28:
ModelSim modes of operation ModelSi
Page 29 and 30:
ModelSim graphic interface overview
Page 31 and 32:
Sections in this document Sections
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Sections in this document UM-33 H -
Page 35 and 36:
Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
Page 53 and 54:
Specifying file properties and proj
Page 55 and 56:
Accessing projects from the command
Page 57 and 58:
3 - Design libraries Chapter conten
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Archives Design library overview UM
Page 61 and 62:
Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
Page 69 and 70:
Importing FPGA libraries Importing
Page 71 and 72:
4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
Page 91 and 92:
Reading and writing hexadecimal num
Page 93 and 94:
VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
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BEGIN FOR i IN 0 TO 1023 LOOP we
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Converting an integer into a bit_ve
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5 - Verilog simulation Chapter cont
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Introduction ModelSim Verilog basic
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Incremental compilation Compiling V
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Library usage Compiling Verilog fil
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Verilog-XL compatible compiler argu
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Compiling Verilog files UM-121 The
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Verilog generate statements Compili
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Naming the optimized design Optimiz
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Optimizing Verilog designs UM-127 I
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Simulating Verilog designs Simulato
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`timescale, -t, and rounding Simula
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Simulating Verilog designs UM-133 T
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Simulating Verilog designs UM-135 M
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+pulse_e_style_onevent +pulse_int_e
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Distributed delay mode In distribut
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System tasks and functions UM-147 a
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File I/O tasks $fclose $fopen $fwri
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System tasks and functions UM-151 T
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Compiler directives Compiler direct
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ModelSim compiler directives The fo
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Determining which memories were imp
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6 - SystemC simulation Chapter cont
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Supported platforms and compiler ve
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Usage flow for SystemC-only designs
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Code modification examples Compilin
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Example 3 Compiling SystemC files U
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Restrictions on compiling with HP a
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Issues with C++ templates Templatiz
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Simulating SystemC designs Loading
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Initialization and cleanup of Syste
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Waveform compare Debugging the desi
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Debugging the design UM-179 The gdb
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Viewing FIFOs SystemC object and ty
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OSCI 2.1 features supported Differe
Page 185 and 186: Troubleshooting SystemC errors UM-1
Page 187 and 188: 7 - Mixed-language simulation Chapt
Page 189 and 190: Usage flow for mixed-language simul
Page 191 and 192: Simulator resolution limit Runtime
Page 193 and 194: Mapping data types Verilog to VHDL
Page 195 and 196: VHDL to Verilog mappings Mapping da
Page 197 and 198: Channels Ports Verilog mapping sc_b
Page 199 and 200: Verilog sc_logic sc_bit bool SuX 'X
Page 201 and 202: SystemC VHDL sc_int, sc_uint bit_ve
Page 203 and 204: VHDL: instantiating Verilog Verilog
Page 205 and 206: The generic type is determined by t
Page 207 and 208: Verilog: instantiating VHDL VHDL in
Page 209 and 210: SystemC: instantiating Verilog Veri
Page 211 and 212: Example #2 SystemC: instantiating V
Page 213 and 214: }; } #endif // Connect ports chip->
Page 215 and 216: Example of parameter use format_cha
Page 217 and 218: SystemC: instantiating VHDL VHDL in
Page 219 and 220: Example SystemC: instantiating VHDL
Page 221 and 222: ); END ringbuf; ARCHITECTURE RTL OF
Page 223 and 224: vgencomp component declaration vgen
Page 225 and 226: 8 - WLF files (datasets) and virtua
Page 227 and 228: Saving a simulation to a WLF file O
Page 229 and 230: Managing multiple datasets WLF file
Page 231 and 232: Saving at intervals with Dataset Sn
Page 233 and 234: Virtual Objects (User-defined buses
Page 235: Virtual regions Virtual types Virtu
Page 239 and 240: Introduction Objects you can view W
Page 241 and 242: Wave window overview UM-241 Here is
Page 243 and 244: List window overview List window ov
Page 245 and 246: Measuring time with cursors in the
Page 247 and 248: Jumping to a signal transition Meas
Page 249 and 250: Zooming the Wave window display Zoo
Page 251 and 252: Searching in the Wave and List wind
Page 253 and 254: Using the Expression Builder for ex
Page 255 and 256: Formatting the Wave window Setting
Page 257 and 258: Formatting the Wave window UM-257 3
Page 259 and 260: Formatting the List window Setting
Page 261 and 262: Saving the window format Saving the
Page 263 and 264: Saving List window data to a file S
Page 265 and 266: Configuring new line triggering in
Page 267 and 268: Configuring new line triggering in
Page 269 and 270: Miscellaneous tasks Examining wavef
Page 271 and 272: Comparison Wizard Waveform Compare
Page 273 and 274: Test Dataset Waveform Compare UM-27
Page 275 and 276: Adding regions Waveform Compare UM-
Page 277 and 278: Clocked comparison Waveform Compare
Page 279 and 280: Viewing differences in the Wave win
Page 281 and 282: Compare icons Waveform Compare UM-2
Page 283 and 284: Comparing hierarchical and flattene
Page 285 and 286: 10 - Generating stimulus with Wavef
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Getting started You can use Wavefor
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Creating waveforms from patterns Cr
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Editing waveforms GR-291 These comm
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Simulating directly from waveform e
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Driving simulation with the saved s
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Saving the waveform editor commands
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11 - Tracing signals with the Dataf
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Adding objects to the window Adding
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Exploring the connectivity of your
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Zooming and panning Zooming with to
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Tracing the source of an unknown (X
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Finding objects by name in the Data
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Printing on Windows platforms Selec
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Symbol mapping Symbol mapping UM-31
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Configuring window options Configur
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12 - Profiling performance and memo
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Getting started Memory allocation p
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Enabling the statistical sampling p
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Interpreting profiler data Interpre
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The Call Tree view Viewing profiler
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Viewing profile details Viewing pro
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Integration with Source windows Int
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Reporting profiler results Reportin
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13 - Measuring code coverage Chapte
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Supported types ModelSim code cover
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Enabling code coverage Enabling cod
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Enabling code coverage UM-339 Next,
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Viewing coverage data in the Source
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Toggle coverage Enabling Toggle cov
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3 Produce the report with the toggl
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Excluding objects from coverage Exc
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end instance Default filter file Ex
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XML output Reporting coverage data
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Instance report with line details R
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Coverage statistics details Conditi
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Coverage statistics details UM-357
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14 - PSL Assertions Chapter content
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PSL assertion language What are ass
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Using cover directives Using assert
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REF2); signal mem_state : memory_st
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} // Check the write cycle property
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Multi-clocked properties and defaul
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Using endpoints in HDL code Example
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Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
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Mistaking a component or module nam
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19 - Value Change Dump (VCD) Files
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Checkpoint/restore and writing VCD
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Example 3 — Mixed-HDL design Firs
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ModelSim VCD commands and VCD tasks
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A VCD file from source to output VH
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x) x* x+ x, $end #300 $dumpon 1! 0"
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Capturing port driver data Supporte
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Example VCD output from vcd dumppor
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20 - Tcl and macros (DO files) Chap
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Tcl commands Tcl commands UM-473 Fo
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Tcl command syntax UM-475 7 If a wo
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set command syntax Tcl command synt
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Variable substitution System comman
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ModelSim Tcl time commands Conversi
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Tcl examples This is an example of
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} if {$windowName == ""} { # Dialog
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Macros (DO files) Creating DO files
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set vFilesExist 1 } shift } if {$vh
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Using the Tcl source command with D
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The Tcl Debugger Starting the debug
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Breakpoints The Tcl Debugger UM-495
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TclPro Debugger TclPro Debugger UM-
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A - ModelSim GUI changes Appendix c
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Main window changes UM-501 See "Cus
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Main window changes UM-503 File > O
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View menu The View menu has been re
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Tools menu The 6.0 Main window Tool
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List window changes File menu The L
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File menu See "Memory windows" (GR-
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View menu The Memory window > View
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Edit menu The Signals window > Edit
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View menu The Source window > File
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B - ModelSim variables Appendix con
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Environment variables Environment v
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Library mapping with environment va
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[Library] library path variables Va
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[vcom] VHDL compiler control variab
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[vsim] simulator control variables
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Preference variables located in INI
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Page 535 and 536:
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Commonly used INI variables Prefere
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Force command defaults Preference v
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Variable precedence Variable preced
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Special considerations for the now
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C - Error and warning messages Appe
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ModelSim message system UM-547 Ther
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Exit codes The table below describe
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Miscellaneous messages Miscellaneou
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Miscellaneous messages UM-553 model
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VSIM license lost Message text Cons
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Suggested action Multiply defined s
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D - Verilog PLI / VPI / DPI Chapter
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Registering PLI applications Regist
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Registering VPI applications Exampl
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Registering DPI applications Regist
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For Windows only: Run a preliminary
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32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
Page 603 and 604:
E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
Page 613 and 614:
Environment variables accessed duri
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Initialization sequence Initializat
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G - Logic Modeling SmartModels Appe
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Creating foreign architectures with
Page 621 and 622:
Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
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H - Logic Modeling hardware models
Page 629 and 630:
Creating foreign architectures with
Page 631 and 632:
Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
Page 637 and 638:
Graphics shall only use or disclose
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Index CR = Command Reference, UM =
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Stop on quit mode UM-414 C Debug se
Page 643 and 644:
mem search CR-204 modelsim CR-206 n
Page 645 and 646:
ange checking in VHDL CR-316, UM-74
Page 647 and 648:
Add Folder GR-47 C Debug setup GR-9
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F -f CR-360 F8 function key UM-607
Page 651 and 652:
Verilog modules UM-125 VHDL subprog
Page 653 and 654:
Memory window GR-169 GUI changes UM
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optimizing Verilog designs design o
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eaders and drivers UM-303 readers c
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adix specifying for examine CR-163
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system tasks VCD UM-461 Verilog UM-
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U -u CR-365 unbound component GR-53
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library clause UM-64 mixed designs
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text editing UM-605 windows Active
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