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ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-128 5 - Verilog simulation<br />

<strong>ModelSim</strong> <strong>SE</strong> User’s <strong>Manual</strong><br />

In these cases, you should optimize the entire design with vopt.<br />

Several switches to vlog can be used to further increase optimizations on gate-level designs.<br />

The +nocheck arguments are described in the Comm<strong>and</strong> Reference under the vlog<br />

comm<strong>and</strong> (CR-358).<br />

You can use the write cell_report comm<strong>and</strong> (CR-421) <strong>and</strong> the -debugCellOpt argument to<br />

the vlog comm<strong>and</strong> (CR-358) to obtain information about which cells have <strong>and</strong> have not been<br />

optimized. write cell_report produces a text file that lists all modules. Modules with<br />

"(cell)" following their names are optimized cells. For example,<br />

Module: top<br />

Architecture: fast<br />

Module: bottom (cell)<br />

Architecture: fast<br />

In this case, both top <strong>and</strong> bottom were compiled with -fast, but top was not optimized <strong>and</strong><br />

bottom was.<br />

The -debugCellOpt argument is used with -fast when compiling the cell library. Using this<br />

argument produces output in the Transcript pane that identifies why certain cells were not<br />

optimized.<br />

Event order <strong>and</strong> optimized designs<br />

As mentioned earlier in the chapter, the Verilog language does not require that the<br />

simulator execute simultaneous events in any particular order. Optimizations performed by<br />

vopt may expose event order dependencies that cause a design to behave differently than<br />

when run unoptimized. Event order dependencies are considered errors <strong>and</strong> should be<br />

corrected (see "Event ordering in Verilog designs" (UM-132) for details).<br />

Timing checks in optimized designs<br />

Timing checks are performed whether you optimize the design or not. In general you'll see<br />

the same results in either case. However, in a cell where there are both interconnect delays<br />

<strong>and</strong> conditional timing checks, you might see different timing check results.<br />

Without vopt the conditional checks are evaluated with non-delayed values, complying<br />

with the original IEEE Std 1364-1995 specification. With vopt the conditional checks will<br />

be evaluated with delayed values, complying with the new IEEE Std 1364-2001<br />

specification.

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