ModelSim SE User's Manual - Electrical and Computer Engineering

UM-132 5 - Verilog simulation
Event ordering in Verilog designs
ModelSim SE User’s Manual
Event-based simulators such as ModelSim may process multiple events at a given
simulation time. The Verilog language is defined such that you cannot explicitly control the
order in which simultaneous events are processed. Unfortunately, some designs rely on a
particular event order, and these designs may behave differently than you expect.
Event queues
Section 5 of the IEEE Std 1364-1995 LRM defines several event queues that determine the
order in which events are evaluated. At the current simulation time, the simulator has the
following pending events:
active events
inactive events
non-blocking assignment update events
monitor events
future events
- inactive events
- non-blocking assignment update events
The LRM dictates that events are processed as follows – 1) all active events are processed;
2) the inactive events are moved to the active event queue and then processed; 3) the
non-blocking events are moved to the active event queue and then processed; 4) the monitor
events are moved to the active queue and then processed; 5) simulation advances to the next
time where there is an inactive event or a non-blocking assignment update event.
Within the active event queue, the events can be processed in any order, and new active
events can be added to the queue in any order. In other words, you cannot control event
order within the active queue. The example below illustrates potential ramifications of this
situation.
Say you have these four statements:
1 always@(q) p = q;
2 always @(q) p2 = not q;
3 always @(p or p2) clk = p and p2;
4 always @(posedge clk)
and current values as follows: q = 0, p = 0, p2=1