ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-504 A - ModelSim GUI changes ModelSim SE User’s Manual 5.8 File > Transcript 6.0 File > Edit >
View menu The View menu has been rearranged a bit, but all the items remain. Main window changes UM-505 View All Windows... becomes View > Debug Windows > All Windows... A sub menu is added to the View menu for all debug windows. For the name changes of the windows, see "Main window changes" (UM-500). 5.8 View > 6.0 View > See "Main window menu bar" (GR-20) for complete menu option details. ModelSim SE User’s Manual
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ModelSim® Advanced Verification an
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Table of Contents 1 - Introduction
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Delta delays . . . . . . . . . . .
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ModelSim Verilog system tasks and f
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VHDL: instantiating SystemC . . . .
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Creating waveforms from patterns .
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14 - PSL Assertions (UM-359) What a
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17 - Signal Spy (UM-417) Introducti
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Starting the debugger . . . . . . .
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Steps in flow . . . . . . . . . . .
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1 - Introduction Chapter contents M
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ModelSim simulation task overview M
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Basic steps for simulation UM-25 Li
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ModelSim modes of operation ModelSi
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ModelSim graphic interface overview
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Sections in this document Sections
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Sections in this document UM-33 H -
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Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
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Specifying file properties and proj
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Accessing projects from the command
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3 - Design libraries Chapter conten
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Archives Design library overview UM
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Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
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Importing FPGA libraries Importing
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4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
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Reading and writing hexadecimal num
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VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
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BEGIN FOR i IN 0 TO 1023 LOOP we
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Converting an integer into a bit_ve
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5 - Verilog simulation Chapter cont
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Introduction ModelSim Verilog basic
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Incremental compilation Compiling V
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Library usage Compiling Verilog fil
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Verilog-XL compatible compiler argu
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Compiling Verilog files UM-121 The
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Verilog generate statements Compili
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Naming the optimized design Optimiz
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Optimizing Verilog designs UM-127 I
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Simulating Verilog designs Simulato
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`timescale, -t, and rounding Simula
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Simulating Verilog designs UM-133 T
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Simulating Verilog designs UM-135 M
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+pulse_e_style_onevent +pulse_int_e
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Distributed delay mode In distribut
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System tasks and functions UM-147 a
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File I/O tasks $fclose $fopen $fwri
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System tasks and functions UM-151 T
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Compiler directives Compiler direct
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ModelSim compiler directives The fo
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Determining which memories were imp
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6 - SystemC simulation Chapter cont
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Supported platforms and compiler ve
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Usage flow for SystemC-only designs
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Code modification examples Compilin
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Example 3 Compiling SystemC files U
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Restrictions on compiling with HP a
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Issues with C++ templates Templatiz
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Simulating SystemC designs Loading
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Initialization and cleanup of Syste
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Waveform compare Debugging the desi
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Debugging the design UM-179 The gdb
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Viewing FIFOs SystemC object and ty
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OSCI 2.1 features supported Differe
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Troubleshooting SystemC errors UM-1
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7 - Mixed-language simulation Chapt
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Usage flow for mixed-language simul
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Simulator resolution limit Runtime
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Mapping data types Verilog to VHDL
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VHDL to Verilog mappings Mapping da
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Channels Ports Verilog mapping sc_b
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Verilog sc_logic sc_bit bool SuX 'X
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SystemC VHDL sc_int, sc_uint bit_ve
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VHDL: instantiating Verilog Verilog
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The generic type is determined by t
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Verilog: instantiating VHDL VHDL in
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SystemC: instantiating Verilog Veri
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Example #2 SystemC: instantiating V
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}; } #endif // Connect ports chip->
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Example of parameter use format_cha
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SystemC: instantiating VHDL VHDL in
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Example SystemC: instantiating VHDL
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); END ringbuf; ARCHITECTURE RTL OF
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vgencomp component declaration vgen
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8 - WLF files (datasets) and virtua
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Saving a simulation to a WLF file O
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Managing multiple datasets WLF file
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Saving at intervals with Dataset Sn
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Virtual Objects (User-defined buses
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Virtual regions Virtual types Virtu
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9 - Waveform analysis Chapter conte
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Introduction Objects you can view W
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Wave window overview UM-241 Here is
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List window overview List window ov
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Measuring time with cursors in the
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Jumping to a signal transition Meas
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Zooming the Wave window display Zoo
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Searching in the Wave and List wind
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Using the Expression Builder for ex
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Formatting the Wave window Setting
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Formatting the Wave window UM-257 3
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Formatting the List window Setting
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Saving the window format Saving the
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Saving List window data to a file S
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Configuring new line triggering in
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Configuring new line triggering in
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Miscellaneous tasks Examining wavef
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Comparison Wizard Waveform Compare
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Test Dataset Waveform Compare UM-27
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Adding regions Waveform Compare UM-
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Clocked comparison Waveform Compare
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Viewing differences in the Wave win
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Compare icons Waveform Compare UM-2
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Comparing hierarchical and flattene
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10 - Generating stimulus with Wavef
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Getting started You can use Wavefor
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Creating waveforms from patterns Cr
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Editing waveforms GR-291 These comm
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Simulating directly from waveform e
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Driving simulation with the saved s
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Saving the waveform editor commands
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11 - Tracing signals with the Dataf
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Adding objects to the window Adding
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Exploring the connectivity of your
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Zooming and panning Zooming with to
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Tracing the source of an unknown (X
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Finding objects by name in the Data
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Printing on Windows platforms Selec
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Symbol mapping Symbol mapping UM-31
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Configuring window options Configur
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12 - Profiling performance and memo
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Getting started Memory allocation p
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Enabling the statistical sampling p
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Interpreting profiler data Interpre
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The Call Tree view Viewing profiler
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Viewing profile details Viewing pro
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Integration with Source windows Int
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Reporting profiler results Reportin
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13 - Measuring code coverage Chapte
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Supported types ModelSim code cover
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Enabling code coverage Enabling cod
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Enabling code coverage UM-339 Next,
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Viewing coverage data in the Source
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Toggle coverage Enabling Toggle cov
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3 Produce the report with the toggl
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Excluding objects from coverage Exc
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end instance Default filter file Ex
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XML output Reporting coverage data
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Instance report with line details R
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Coverage statistics details Conditi
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Coverage statistics details UM-357
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14 - PSL Assertions Chapter content
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PSL assertion language What are ass
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Using cover directives Using assert
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REF2); signal mem_state : memory_st
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} // Check the write cycle property
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Multi-clocked properties and defaul
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Using endpoints in HDL code Example
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Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
Page 453 and 454: Mistaking a component or module nam
Page 455 and 456: 19 - Value Change Dump (VCD) Files
Page 457 and 458: Checkpoint/restore and writing VCD
Page 459 and 460: Example 3 — Mixed-HDL design Firs
Page 461 and 462: ModelSim VCD commands and VCD tasks
Page 463 and 464: A VCD file from source to output VH
Page 465 and 466: x) x* x+ x, $end #300 $dumpon 1! 0"
Page 467 and 468: Capturing port driver data Supporte
Page 469 and 470: Example VCD output from vcd dumppor
Page 471 and 472: 20 - Tcl and macros (DO files) Chap
Page 473 and 474: Tcl commands Tcl commands UM-473 Fo
Page 475 and 476: Tcl command syntax UM-475 7 If a wo
Page 477 and 478: set command syntax Tcl command synt
Page 479 and 480: Variable substitution System comman
Page 481 and 482: ModelSim Tcl time commands Conversi
Page 483 and 484: Tcl examples This is an example of
Page 485 and 486: } if {$windowName == ""} { # Dialog
Page 487 and 488: Macros (DO files) Creating DO files
Page 489 and 490: set vFilesExist 1 } shift } if {$vh
Page 491 and 492: Using the Tcl source command with D
Page 493 and 494: The Tcl Debugger Starting the debug
Page 495 and 496: Breakpoints The Tcl Debugger UM-495
Page 497 and 498: TclPro Debugger TclPro Debugger UM-
Page 499 and 500: A - ModelSim GUI changes Appendix c
Page 501 and 502: Main window changes UM-501 See "Cus
Page 503: Main window changes UM-503 File > O
Page 507 and 508: Tools menu The 6.0 Main window Tool
Page 509 and 510: List window changes File menu The L
Page 511 and 512: File menu See "Memory windows" (GR-
Page 513 and 514: View menu The Memory window > View
Page 515 and 516: Edit menu The Signals window > Edit
Page 517 and 518: View menu The Source window > File
Page 519 and 520: B - ModelSim variables Appendix con
Page 521 and 522: Environment variables Environment v
Page 523 and 524: Library mapping with environment va
Page 525 and 526: [Library] library path variables Va
Page 527 and 528: [vcom] VHDL compiler control variab
Page 529 and 530: [vsim] simulator control variables
Page 531 and 532: Preference variables located in INI
Page 537 and 538: Commonly used INI variables Prefere
Page 539 and 540: Force command defaults Preference v
Page 541 and 542: Variable precedence Variable preced
Page 543 and 544: Special considerations for the now
Page 545 and 546: C - Error and warning messages Appe
Page 547 and 548: ModelSim message system UM-547 Ther
Page 549 and 550: Exit codes The table below describe
Page 551 and 552: Miscellaneous messages Miscellaneou
Page 553 and 554: Miscellaneous messages UM-553 model
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VSIM license lost Message text Cons
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Suggested action Multiply defined s
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D - Verilog PLI / VPI / DPI Chapter
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Registering PLI applications Regist
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Registering VPI applications Exampl
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Registering DPI applications Regist
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For Windows only: Run a preliminary
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32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
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E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
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Environment variables accessed duri
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Initialization sequence Initializat
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G - Logic Modeling SmartModels Appe
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Creating foreign architectures with
Page 621 and 622:
Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
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H - Logic Modeling hardware models
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Creating foreign architectures with
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Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
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Graphics shall only use or disclose
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Index CR = Command Reference, UM =
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Stop on quit mode UM-414 C Debug se
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mem search CR-204 modelsim CR-206 n
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ange checking in VHDL CR-316, UM-74
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Add Folder GR-47 C Debug setup GR-9
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F -f CR-360 F8 function key UM-607
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Verilog modules UM-125 VHDL subprog
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Memory window GR-169 GUI changes UM
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optimizing Verilog designs design o
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eaders and drivers UM-303 readers c
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adix specifying for examine CR-163
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system tasks VCD UM-461 Verilog UM-
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U -u CR-365 unbound component GR-53
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library clause UM-64 mixed designs
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text editing UM-605 windows Active
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