ModelSim SE User's Manual - Electrical and Computer Engineering

VHDL to Verilog mappings
Mapping data types UM-195
For Verilog states with ambiguous strength:
bit receives '0'
std_logic receives 'X' if either the 0 or 1 st rength component is greater than or equal to
strong strength
std_logic receives 'W' if both the 0 and 1 strength components are less than strong
strength
VHDL generics
VHDL type Verilog type
integer integer or real
real integer or real
time integer or real
physical integer or real
enumeration integer or real
string string literal
When a scalar type receives a real value, the real is converted to an integer by truncating
the decimal portion.
Type time is treated specially: the Verilog number is converted to a time value according
to the ‘timescale directive of the module.
Physical and enumeration types receive a value that corresponds to the position number
indicated by the Verilog number. In VHDL this is equivalent to T'VAL(P), where T is the
type, VAL is the predefined function attribute that returns a value given a position number,
and P is the position number.
VHDL type bit is mapped to Verilog states as follows:
bit Verilog
'0' St0
'1' St1
VHDL type std_logic is mapped to Verilog states as follows:
std_logic Verilog
'U' StX
'X' StX
'0' St0
ModelSim SE User’s Manual