ModelSim SE User's Manual - Electrical and Computer Engineering

vgencomp component declaration
vgencomp (CR-330) generates a component declaration according to these rules:
Port clause
VHDL: instantiating SystemC UM-223
A port clause is generated if the module has ports. A corresponding VHDL port is defined
for each named SystemC port.
You can set the VHDL port type to bit or std_logic. If the SystemC port has a range, then
the VHDL port type is bit_vector or std_logic_vector.
Examples
Exporting SystemC modules
sccom -link
SystemC identifier VHDL identifier
_topmod \_topmod\
SystemC port VHDL port
sc_inp1; p1 : in std_logic;
sc_outp2; p2 : out std_logic_vector(7 downto 0);
sc_inoutp3; p3 : inout std_logic_vector(7 downto 0)
Configuration declarations are allowed to reference SystemC modules in the entity aspects
of component configurations. However, the configuration declaration cannot extend into a
SystemC instance to configure the instantiations within the SystemC module.
To be able to instantiate a SystemC module within VHDL (or use a SystemC module as a
top level module), the module must be exported.
Assume a SystemC module named transceiver exists, and that it is declared in header file
transceiver.h. Then the module is exported by placing the following code in a .cpp file:
#include "transceiver.h"
SC_MODULE_EXPORT(transceiver);
The sccom -link command collects the object files created in the work library, and uses
them to build a shared library (.so) in the current work library. If you have changed your
SystemC source code and recompiled it using sccom, then you must run sccom -link before
invoking vsim. Otherwise your changes to the code are not recognized by the simulator.
Generic support for VHDL instantiating SystemC
Support for generics is available in a workaround flow for the current release. For
workaround flow details, please refer to systemc_generics.note located in the
/modeltech/docs/technotes directory.
ModelSim SE User’s Manual