ModelSim SE User's Manual - Electrical and Computer Engineering

UM-418 17 - Signal Spy
Introduction
Designed for testbenches
ModelSim SE User’s Manual
The Verilog language allows access to any signal from any other hierarchical block without
having to route it via the interface. This means you can use hierarchical notation to either
assign or determine the value of a signal in the design hierarchy from a testbench. This
capability fails when a Verilog testbench attempts to reference a signal in a VHDL block
or reference a signal in a Verilog block through a VHDL level of hierarchy.
This limitation exists because VHDL does not allow hierarchical notation. In order to
reference internal hierarchical signals, you have to resort to defining signals in a global
package and then utilize those signals in the hierarchical blocks in question. But, this
requires that you keep making changes depending on the signals that you want to reference.
The Signal Spy procedures and system tasks overcome the aforementioned limitations.
They allow you to monitor (spy), drive, force, or release hierarchical objects in a VHDL or
mixed design.
The VHDL procedures are provided via the "Util package" (UM-96) within the modelsim_lib
library. To access the procedures you would add lines like the following to your VHDL
code:
library modelsim_lib;
use modelsim_lib.util.all;
The Verilog tasks are available as built-in "System tasks and functions" (UM-146). The table
below shows the VHDL procedures and their corresponding Verilog system tasks.
VHDL procedures Verilog system tasks
init_signal_driver (UM-419) $init_signal_driver (UM-429)
init_signal_spy (UM-422) $init_signal_spy (UM-432)
In this example, the value of /top/uut/
inst1/sig1 is mirrored onto /top/
top_sig1. signal_force (UM-425)
$signal_force (UM-434)
signal_release (UM-427) $signal_release (UM-436)
Signal Spy limits the portability of your code. HDL code with Signal Spy procedures or
tasks works only in ModelSim, not other simulators. We therefore recommend using Signal
Spy only in testbenches, where portability is less of a concern, and the need for such a tool
is more applicable.