ModelSim SE User's Manual - Electrical and Computer Engineering

Creating foreign architectures with sm_entity
VHDL SmartModel interface UM-619
The ModelSim sm_entity tool automatically creates entities and foreign architectures for
SmartModels. Its usage is as follows:
Syntax
sm_entity
[-] [-xe] [-xa] [-c] [-all] [-v] [-93] [...]
Arguments
-
Read SmartModel names from standard input.
-xe
Do not generate entity declarations.
-xa
Do not generate architecture bodies.
-c
Generate component declarations.
-all
Select all models installed in the SmartModel library.
-v
Display progress messages.
-93
Use extended identifiers where needed.
Name of a SmartModel (see the SmartModel library documentation for details on
SmartModel names).
By default, the sm_entity tool writes an entity and foreign architecture to stdout for each
SmartModel name listed on the command line. Optionally, you can include the component
declaration (-c), exclude the entity (-xe), and exclude the architecture (-xa).
The simplest way to prepare SmartModels for use with ModelSim VHDL is to generate the
entities and foreign architectures for all installed SmartModels, and compile them into a
library named lmc. This is easily accomplished with the following commands:
% sm_entity -all > sml.vhd
% vlib lmc
% vcom -work lmc sml.vhd
To instantiate the SmartModels in your VHDL design, you also need to generate
component declarations for the SmartModels. Add these component declarations to a
package named sml (for example), and compile the package into the lmc library:
% sm_entity -all -c -xe -xa > smlcomp.vhd
ModelSim SE User’s Manual