ModelSim SE User's Manual - Electrical and Computer Engineering

UM-364 14 - PSL Assertions
Embedding assertions in your code
Syntax
Restrictions
Example
ModelSim SE User’s Manual
One way of looking at assertions is as design documentation. In other words, anywhere you
would normally write a comment to capture pre-conditions, constraints or other
assumptions as well as to document the proper functionality of a module, process, or
subprogram, use assertions to capture the information instead.
PSL assertions are embedded using metacomments prefixed with 'psl'. For example:
-- psl sequence s0 is {b0; b1; b2};
The PSL statement can be multi-line. For example:
-- psl sequence s0 is
-- {b0; b1; b2};
Note that the second line did not require a 'psl' prefix. Once in PSL context, the parser will
remain there until a PSL statement is terminated with a semicolon (';').
Embedded assertions have the following restriction as to where they can be embedded:
Assertions can be embedded anywhere inside a Verilog module except initial blocks,
always blocks, tasks, and functions. They cannot be embedded in UDPs.
Assertions can be embedded only in declarative and statement regions of a VHDL entity
or architecture body.
In a statement region, assertions can app ear at places where concurrent statements may
appear. If they appear in a sequential statement, ModelSim will generate an error.
Assertions cannot be embedded in VHDL procedures and functions.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.constants.all;
entity dram_control is
generic ( BUG : Boolean := TRUE );
port ( clk : IN std_logic;
reset_n : IN std_logic;
as_n : IN std_logic;
addr_in : IN std_logic_vector(AIN-1 downto 0);
addr_out: OUT std_logic_vector(AOUT-1 downto 0);
rw : IN std_logic; -- 1 to read; 0 to write
we_n : OUT std_logic;
ras_n : OUT std_logic;
cas_n : OUT std_logic;
ack : OUT std_logic );
end entity dram_control;
architecture RTL of dram_control is
type memory_state is (IDLE, MEM_ACCESS, SWITCH, RAS_CAS, OP_ACK, REF1,