ModelSim SE User's Manual - Electrical and Computer Engineering

UM-392 15 - Functional coverage with PSL and ModelSim
Sample report output
ModelSim SE User’s Manual
The following is an example of the standard report file output:
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Name Design Design File(Line) Count Status
Unit UnitType
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/alpha/cover__0 alpha Verilog test.v(48) 6 Covered
/alpha/cover__1 alpha Verilog test.v(49) 6 Covered
DESIGN UNIT: alpha COVERAGE: 100.0% COVERS: 2
/alpha/inst1/cover__0 beta Verilog test.v(66) 6 Covered
/alpha/inst1/cover__1 beta Verilog test.v(67) 6 Covered
/alpha/inst2/cover__0 beta Verilog test.v(66) 6 Covered
/alpha/inst2/cover__1 beta Verilog test.v(67) 6 Covered
DESIGN UNIT: beta COVERAGE: 100.0% COVERS: 4
/alpha/inst1/instA/cover__0 gamma Verilog test.v(82) 6 Covered
/alpha/inst1/instA/cover__1 gamma Verilog test.v(83) 6 Covered
/alpha/inst1/instA/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst1/instA/cover__3 gamma Verilog test.v(87) 0 ZERO
/alpha/inst1/instB/cover__0 gamma Verilog test.v(82) 6 Covered
/alpha/inst1/instB/cover__1 gamma Verilog test.v(83) 6 Covered
/alpha/inst1/instB/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst1/instB/cover__3 gamma Verilog test.v(87) 0 ZERO
/alpha/inst1/instC/cover__0 gamma Verilog test.v(82) 0 ZERO
/alpha/inst1/instC/cover__1 gamma Verilog test.v(83) 0 ZERO
/alpha/inst1/instC/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst1/instC/cover__3 gamma Verilog test.v(87) 0 ZERO
/alpha/inst2/instA/cover__0 gamma Verilog test.v(82) 6 Covered
/alpha/inst2/instA/cover__1 gamma Verilog test.v(83) 6 Covered
/alpha/inst2/instA/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst2/instA/cover__3 gamma Verilog test.v(87) 0 ZERO
/alpha/inst2/instB/cover__0 gamma Verilog test.v(82) 6 Covered
/alpha/inst2/instB/cover__1 gamma Verilog test.v(83) 6 Covered
/alpha/inst2/instB/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst2/instB/cover__3 gamma Verilog test.v(87) 0 ZERO
/alpha/inst2/instC/cover__0 gamma Verilog test.v(82) 0 ZERO
/alpha/inst2/instC/cover__1 gamma Verilog test.v(83) 0 ZERO
/alpha/inst2/instC/cover__2 gamma Verilog test.v(86) 0 ZERO
/alpha/inst2/instC/cover__3 gamma Verilog test.v(87) 0 ZERO
DESIGN UNIT: gamma COVERAGE: 33.3% COVERS: 24
TOTAL COVERAGE: 46.7% COVERS: 30
Formatting output in XML
If you select Use XML Format in the Functional Coverage Report dialog, ModelSim
marks-up the output with XML tags. The table below describes the XML tags:
Tag Meaning
denotes the entire report
denotes a design unit
denotes aggregate coverage as a percentage, for design unit and design
(if aggregated coverage is selected in the report)