ModelSim SE User's Manual - Electrical and Computer Engineering

Tcl examples
This is an example of using the Tcl while loop to copy a list from variable a to variable b,
reversing the order of the elements along the way:
set b [list]
set i [expr {[llength $a] - 1}]
while {$i >= 0} {
lappend b [lindex $a $i]
incr i -1
}
This example uses the Tcl for command to copy a list from variable a to variable b,
reversing the order of the elements along the way:
set b [list]
for {set i [expr {[llength $a] - 1}]} {$i >= 0} {incr i -1} {
lappend b [lindex $a $i]
}
Tcl examples UM-483
This example uses the Tcl foreach command to copy a list from variable a to variable b,
reversing the order of the elements along the way (the foreach command iterates over all of
the elements of a list):
set b [list]
foreach i $a { set b [linsert $b 0 $i] }
This example shows a list reversal as above, this time aborting on a particular element using
the Tcl break command:
set b [list]
foreach i $a {
if {$i = "ZZZ"} break
set b [linsert $b 0 $i]
}
This example is a list reversal that skips a particular element by using the Tcl continue
command:
set b [list]
foreach i $a {
if {$i = "ZZZ"} continue
set b [linsert $b 0 $i]
}
The next example works in UNIX only. In a Windows environment, the Tcl exec command
will execute compiled files only, not system commands.) The example shows how you can
access system information and transfer it into VHDL variables or signals and Verilog nets
or registers. When a particular HDL source breakpoint occurs, a Tcl function is called that
gets the date and time and deposits it into a VHDL signal of type STRING. If a particular
environment variable (DO_ECHO) is set, the function also echoes the new date and time
to the transcript file by examining the VHDL variable.
(in VHDL source):
signal datime : string(1 to 28) := " ";# 28 spaces
ModelSim SE User’s Manual