ModelSim SE User's Manual - Electrical and Computer Engineering

UM-630 H - Logic Modeling hardware models
ModelSim SE User’s Manual
end;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
A7 : in std_logic;
A8 : in std_logic;
A9 : in std_logic;
A10 : in std_logic;
A11 : in std_logic;
A12 : in std_logic;
A13 : in std_logic;
A14 : in std_logic;
A15 : in std_logic;
CS : in std_logic;
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
O4 : out std_logic;
O5 : out std_logic;
O6 : out std_logic;
O7 : out std_logic;
W : inout std_logic );
architecture Hardware of cy7c285 is
attribute FOREIGN : STRING;
attribute FOREIGN of Hardware : architecture is
"hm_init $MODEL_TECH/libhm.sl ; CY7C285.MDL";
begin
end Hardware;
Entity details
The entity name is the hardware model name (you can manually change this name if you
like).
The port names are the same as the hardware model port names (these names must not be
changed). If the hardware model port name is not a valid VHDL identifier, then
hm_entity issues an error message. If hm_entity is invoked with the -93 option, then the
identifier is converted to an extended identifier, and the resulting entity must also be
compiled with the -93 option. Another option is to create a pin-name mapping file.
Consult the Logic Modeling documentation from Synopsys for details.
The port types are std_logic. This data type supports the full range of hardware model
logic states.
The DelayRange generic selects minimum, typical, or maximum delay values. Valid
values are "min", "typ", or "max" (the strings are not case-sensitive). The default is
"max".