ModelSim SE User's Manual - Electrical and Computer Engineering

VHDL: instantiating Verilog
Verilog instantiation criteria
Component declaration
VHDL: instantiating Verilog UM-203
Once you have generated a component declaration for a Verilog module, you can
instantiate the component just like any other VHDL component. You can reference a
Verilog module in the entity aspect of a component configuration – all you need to do is
specify a module name instead of an entity name. You can also specify an optional
secondary name for an optimized sub-module. Further, you can reference a Verilog
configuration in the configuration aspect of a VHDL component configuration - just
specify a Verilog configuration name instead of a VHDL configuration name.
A Verilog design unit may be instantiated within VHDL if it meets the following criteria:
The design unit is a module or configuration. UDPs are not allowed.
The ports are named ports (see "Modules with unnamed ports" (UM-206) below).
The ports are not connected to bidirectional pass switches (it is not possible to handle pass
switches in VHDL).
A Verilog module that is compiled into a library can be referenced from a VHDL design as
though the module is a VHDL entity. Likewise, a Verilog configuration can be referenced
as though it were a VHDL configuration.
The interface to the module can be extracted from the library in the form of a component
declaration by running vgencomp (CR-330). Given a library and module name, vgencomp
(CR-330) writes a component declaration to standard output.
The default component port types are:
std_logic
std_logic_vector
Optionally, you can choose:
bit and bit_vector
vl_logic and vl_logic_vector
VHDL and Verilog identifiers
The VHDL identifiers for the component name, port names, and generic names are the
same as the Verilog identifiers for the module name, port names, and parameter names. If
a Verilog identifier is not a valid VHDL 1076-1987 identifier, it is converted to a VHDL
1076-1993 extended identifier (in which case you must compile the VHDL with the -93 or
higher switch). Any uppercase letters in Verilog identifiers are converted to lowercase in
the VHDL identifier, except in the following cases:
The Verilog module was compiled with the -93 switch. This means vgencomp (CR-330)
should use VHDL 1076-1993 extended identifiers in the component declaration to
preserve case in the Verilog identifiers that contain uppercase letters.
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