ModelSim SE User's Manual - Electrical and Computer Engineering

UM-436 17 - Signal Spy
$signal_release
Syntax
Returns
Arguments
Related tasks
Limitations
ModelSim SE User’s Manual
The $signal_release() system task releases any force that was applied to an existing VHDL
signal or Verilog register/net (called the dest_object). This allows you to release signals,
registers, or nets at any level of the design hierarchy from within a Verilog module (e.g., a
testbench).
A $signal_release works the same as the noforce command (CR-208). $signal_release can
be called concurrently or sequentially in a process.
Nothing
$signal_release( dest_object, verbose )
Name Type Description
dest_object string Required. A full hierarchical path (or relative
path with reference to the calling block) to an
existing VHDL signal or Verilog register/net.
Use the path separator to which your
simulation is set (i.e., "/" or "."). A full
hierarchical path must begin with a "/" or ".".
The path must be contained within double
quotes.
verbose integer Optional. Possible values are 0 or 1. Specifies
whether you want a message reported in the
Transcript stating that the signal is being
released and the time of the release. Default is
0, no message.
$init_signal_driver (UM-429), $init_signal_spy (UM-432), $signal_force (UM-434)
You cannot release a bit or slice of a register; you can release only the entire register.