ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-520 B - ModelSim variables Variable settings report Personal preferences ModelSim SE User’s Manual The report command (CR-244) returns a list of current settings for either the simulator state, or simulator control variables. Use the following commands at either the ModelSim or VSIM prompt: report simulator state report simulator control The simulator control variables reported by the report simulator control command can be set interactively using the Tcl set command (UM-477). There are several preferences stored by ModelSim on a personal basis, independent of modelsim.ini or modelsim.tcl files. These preferences are stored in $(HOME)/.modelsim on UNIX and in the Windows Registry under HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim. Among these preferences are: mti_ask_LBViewTypes, mti_ask_LBViewPath, mti_ask_LBViewLoadable Settings for the Customize Library View dialog. Determine the view of the Library tab in the Workspace pane. mti_pane_cnt , mti_pane_size, pane_#, pane_percent Determine the layout of various panes in the Main window. open_workspace Setting for whether or not to display the Workspace pane. pinit Project Initialization state (one of: Welcome | OpenLast | NoWelcome). This determines whether the Welcome To ModelSim dialog box appears when you invoke the tool. project_history Project history. printersetup All setup parameters related to printing (i.e., current printer, etc.). transcriptpercent The size of the Transcript pane. Expressed as a percentage of the width of the Main window. The HKEY_CURRENT_USER key is unique for each user Login on Windows NT. Returning to the original ModelSim defaults If you would like to return ModelSim’s interface to its original state, simply rename or delete the existing modelsim.tcl and modelsim.ini files. ModelSim will use pref.tcl for GUI preferences and make a copy of /modeltech/modelsim.ini to use the next time ModelSim is invoked without an existing project (if you start a new project the new MPF file will use the settings in the new modelsim.ini file).
Environment variables Environment variables UM-521 Before compiling or simulating, several environment variables may be set to provide the functions described in the table below. The variables are in the autoexec.bat file on Windows 98/Me machines, and set through the System control panel on NT/2000/XP machines. For UNIX, the variables are typically found in the .login script. The LM_LICENSE_FILE variable is required; all others are optional. Variable Description DOPATH used by ModelSim to search for DO files (macros); consists of a colon-separated (semi-colon for Windows) list of paths to directories; this environment variable can be overridden by the DOPATH Tcl preference variable The DOPATH environment variable isn’t accessible when you invoke vsim from a Unix shell or from a Windows command prompt. It is accessible once ModelSim or vsim is invoked. If you need to invoke from a shell or command line and use the DOPATH environment variable, use the following syntax: vsim -do "do " EDITOR specifies the editor to invoke with the edit command (CR-157) HOME used by ModelSim to look for an optional graphical preference file and optional location map file; see: "Preference variables located in INI files" (UM-524) LM_LICENSE_FILE used by the ModelSim license file manager to find the location of the license file; may be a colon-separated (semi-colon for Windows) set of paths, including paths to other vendor license files; REQUIRED MODEL_TECH set by all ModelSim tools to the directory in which the binary executable resides; DO NOT SET THIS VARIABLE! MODEL_TECH_TCL used by ModelSim to find Tcl libraries for Tcl/Tk 8.3 and vsim; may also be used to specify a startup DO file; defaults to /modeltech/../tcl; may be set to an alternate path MGC_LOCATION_MAP used by ModelSim tools to find source files based on easily reallocated "soft" paths; optional; see the Tcl variables: SourceDir and SourceMap MODELSIM used by all ModelSim tools to find the modelsim.ini file; consists of a path including the file name. An alternative use of this variable is to set it to the path of a project file (/.mpf). This allows you to use project settings with command line tools. However, if you do this, the .mpf file will replace modelsim.ini as the initialization file for all ModelSim tools. MODELSIM_TCL used by ModelSim to look for an optional graphical preference file; can be a colon-separated (UNIX) or semi-colon separated (Windows) list of file paths MTI_COSIM_TRACE creates an mti_trace_cosim file containing debugging information about FLI/PLI/ VPI function calls; set to any value before invoking the simulator. ModelSim SE User’s Manual
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ModelSim® Advanced Verification an
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Table of Contents 1 - Introduction
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Delta delays . . . . . . . . . . .
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ModelSim Verilog system tasks and f
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VHDL: instantiating SystemC . . . .
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Creating waveforms from patterns .
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14 - PSL Assertions (UM-359) What a
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17 - Signal Spy (UM-417) Introducti
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Starting the debugger . . . . . . .
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Steps in flow . . . . . . . . . . .
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1 - Introduction Chapter contents M
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ModelSim simulation task overview M
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Basic steps for simulation UM-25 Li
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ModelSim modes of operation ModelSi
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ModelSim graphic interface overview
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Sections in this document Sections
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Sections in this document UM-33 H -
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Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
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Specifying file properties and proj
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Accessing projects from the command
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3 - Design libraries Chapter conten
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Archives Design library overview UM
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Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
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Importing FPGA libraries Importing
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4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
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Reading and writing hexadecimal num
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VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
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BEGIN FOR i IN 0 TO 1023 LOOP we
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Converting an integer into a bit_ve
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5 - Verilog simulation Chapter cont
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Introduction ModelSim Verilog basic
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Incremental compilation Compiling V
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Library usage Compiling Verilog fil
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Verilog-XL compatible compiler argu
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Compiling Verilog files UM-121 The
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Verilog generate statements Compili
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Naming the optimized design Optimiz
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Optimizing Verilog designs UM-127 I
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Simulating Verilog designs Simulato
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`timescale, -t, and rounding Simula
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Simulating Verilog designs UM-133 T
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Simulating Verilog designs UM-135 M
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+pulse_e_style_onevent +pulse_int_e
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Distributed delay mode In distribut
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System tasks and functions UM-147 a
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File I/O tasks $fclose $fopen $fwri
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System tasks and functions UM-151 T
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Compiler directives Compiler direct
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ModelSim compiler directives The fo
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Determining which memories were imp
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6 - SystemC simulation Chapter cont
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Supported platforms and compiler ve
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Usage flow for SystemC-only designs
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Code modification examples Compilin
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Example 3 Compiling SystemC files U
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Restrictions on compiling with HP a
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Issues with C++ templates Templatiz
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Simulating SystemC designs Loading
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Initialization and cleanup of Syste
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Waveform compare Debugging the desi
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Debugging the design UM-179 The gdb
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Viewing FIFOs SystemC object and ty
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OSCI 2.1 features supported Differe
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Troubleshooting SystemC errors UM-1
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7 - Mixed-language simulation Chapt
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Usage flow for mixed-language simul
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Simulator resolution limit Runtime
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Mapping data types Verilog to VHDL
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VHDL to Verilog mappings Mapping da
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Channels Ports Verilog mapping sc_b
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Verilog sc_logic sc_bit bool SuX 'X
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SystemC VHDL sc_int, sc_uint bit_ve
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VHDL: instantiating Verilog Verilog
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The generic type is determined by t
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Verilog: instantiating VHDL VHDL in
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SystemC: instantiating Verilog Veri
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Example #2 SystemC: instantiating V
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}; } #endif // Connect ports chip->
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Example of parameter use format_cha
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SystemC: instantiating VHDL VHDL in
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Example SystemC: instantiating VHDL
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); END ringbuf; ARCHITECTURE RTL OF
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vgencomp component declaration vgen
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8 - WLF files (datasets) and virtua
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Saving a simulation to a WLF file O
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Managing multiple datasets WLF file
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Saving at intervals with Dataset Sn
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Virtual Objects (User-defined buses
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Virtual regions Virtual types Virtu
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9 - Waveform analysis Chapter conte
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Introduction Objects you can view W
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Wave window overview UM-241 Here is
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List window overview List window ov
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Measuring time with cursors in the
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Jumping to a signal transition Meas
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Zooming the Wave window display Zoo
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Searching in the Wave and List wind
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Using the Expression Builder for ex
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Formatting the Wave window Setting
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Formatting the Wave window UM-257 3
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Formatting the List window Setting
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Saving the window format Saving the
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Saving List window data to a file S
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Configuring new line triggering in
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Configuring new line triggering in
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Miscellaneous tasks Examining wavef
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Comparison Wizard Waveform Compare
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Test Dataset Waveform Compare UM-27
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Adding regions Waveform Compare UM-
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Clocked comparison Waveform Compare
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Viewing differences in the Wave win
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Compare icons Waveform Compare UM-2
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Comparing hierarchical and flattene
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10 - Generating stimulus with Wavef
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Getting started You can use Wavefor
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Creating waveforms from patterns Cr
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Editing waveforms GR-291 These comm
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Simulating directly from waveform e
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Driving simulation with the saved s
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Saving the waveform editor commands
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11 - Tracing signals with the Dataf
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Adding objects to the window Adding
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Exploring the connectivity of your
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Zooming and panning Zooming with to
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Tracing the source of an unknown (X
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Finding objects by name in the Data
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Printing on Windows platforms Selec
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Symbol mapping Symbol mapping UM-31
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Configuring window options Configur
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12 - Profiling performance and memo
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Getting started Memory allocation p
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Enabling the statistical sampling p
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Interpreting profiler data Interpre
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The Call Tree view Viewing profiler
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Viewing profile details Viewing pro
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Integration with Source windows Int
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Reporting profiler results Reportin
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13 - Measuring code coverage Chapte
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Supported types ModelSim code cover
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Enabling code coverage Enabling cod
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Enabling code coverage UM-339 Next,
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Viewing coverage data in the Source
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Toggle coverage Enabling Toggle cov
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3 Produce the report with the toggl
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Excluding objects from coverage Exc
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end instance Default filter file Ex
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XML output Reporting coverage data
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Instance report with line details R
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Coverage statistics details Conditi
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Coverage statistics details UM-357
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14 - PSL Assertions Chapter content
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PSL assertion language What are ass
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Using cover directives Using assert
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REF2); signal mem_state : memory_st
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} // Check the write cycle property
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Multi-clocked properties and defaul
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Using endpoints in HDL code Example
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Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
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Mistaking a component or module nam
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19 - Value Change Dump (VCD) Files
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Checkpoint/restore and writing VCD
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Example 3 — Mixed-HDL design Firs
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ModelSim VCD commands and VCD tasks
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A VCD file from source to output VH
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x) x* x+ x, $end #300 $dumpon 1! 0"
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Capturing port driver data Supporte
Page 469 and 470: Example VCD output from vcd dumppor
Page 471 and 472: 20 - Tcl and macros (DO files) Chap
Page 473 and 474: Tcl commands Tcl commands UM-473 Fo
Page 475 and 476: Tcl command syntax UM-475 7 If a wo
Page 477 and 478: set command syntax Tcl command synt
Page 479 and 480: Variable substitution System comman
Page 481 and 482: ModelSim Tcl time commands Conversi
Page 483 and 484: Tcl examples This is an example of
Page 485 and 486: } if {$windowName == ""} { # Dialog
Page 487 and 488: Macros (DO files) Creating DO files
Page 489 and 490: set vFilesExist 1 } shift } if {$vh
Page 491 and 492: Using the Tcl source command with D
Page 493 and 494: The Tcl Debugger Starting the debug
Page 495 and 496: Breakpoints The Tcl Debugger UM-495
Page 497 and 498: TclPro Debugger TclPro Debugger UM-
Page 499 and 500: A - ModelSim GUI changes Appendix c
Page 501 and 502: Main window changes UM-501 See "Cus
Page 503 and 504: Main window changes UM-503 File > O
Page 505 and 506: View menu The View menu has been re
Page 507 and 508: Tools menu The 6.0 Main window Tool
Page 509 and 510: List window changes File menu The L
Page 511 and 512: File menu See "Memory windows" (GR-
Page 513 and 514: View menu The Memory window > View
Page 515 and 516: Edit menu The Signals window > Edit
Page 517 and 518: View menu The Source window > File
Page 519: B - ModelSim variables Appendix con
Page 523 and 524: Library mapping with environment va
Page 525 and 526: [Library] library path variables Va
Page 527 and 528: [vcom] VHDL compiler control variab
Page 529 and 530: [vsim] simulator control variables
Page 531 and 532: Preference variables located in INI
Page 537 and 538: Commonly used INI variables Prefere
Page 539 and 540: Force command defaults Preference v
Page 541 and 542: Variable precedence Variable preced
Page 543 and 544: Special considerations for the now
Page 545 and 546: C - Error and warning messages Appe
Page 547 and 548: ModelSim message system UM-547 Ther
Page 549 and 550: Exit codes The table below describe
Page 551 and 552: Miscellaneous messages Miscellaneou
Page 553 and 554: Miscellaneous messages UM-553 model
Page 555 and 556: VSIM license lost Message text Cons
Page 557 and 558: Suggested action Multiply defined s
Page 559 and 560: D - Verilog PLI / VPI / DPI Chapter
Page 561 and 562: Registering PLI applications Regist
Page 563 and 564: Registering VPI applications Exampl
Page 565 and 566: Registering DPI applications Regist
Page 567 and 568: For Windows only: Run a preliminary
Page 569 and 570: 32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
Page 603 and 604:
E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
Page 613 and 614:
Environment variables accessed duri
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Initialization sequence Initializat
Page 617 and 618:
G - Logic Modeling SmartModels Appe
Page 619 and 620:
Creating foreign architectures with
Page 621 and 622:
Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
Page 627 and 628:
H - Logic Modeling hardware models
Page 629 and 630:
Creating foreign architectures with
Page 631 and 632:
Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
Page 637 and 638:
Graphics shall only use or disclose
Page 639 and 640:
Index CR = Command Reference, UM =
Page 641 and 642:
Stop on quit mode UM-414 C Debug se
Page 643 and 644:
mem search CR-204 modelsim CR-206 n
Page 645 and 646:
ange checking in VHDL CR-316, UM-74
Page 647 and 648:
Add Folder GR-47 C Debug setup GR-9
Page 649 and 650:
F -f CR-360 F8 function key UM-607
Page 651 and 652:
Verilog modules UM-125 VHDL subprog
Page 653 and 654:
Memory window GR-169 GUI changes UM
Page 655 and 656:
optimizing Verilog designs design o
Page 657 and 658:
eaders and drivers UM-303 readers c
Page 659 and 660:
adix specifying for examine CR-163
Page 661 and 662:
system tasks VCD UM-461 Verilog UM-
Page 663 and 664:
U -u CR-365 unbound component GR-53
Page 665 and 666:
library clause UM-64 mixed designs
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text editing UM-605 windows Active
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