ModelSim SE User's Manual - Electrical and Computer Engineering

UM-122 5 - Verilog simulation
Verilog configurations
ModelSim SE User’s Manual
The Verilog 2001 specification added configurations. Configurations specify how a design
is "assembled" during the elaboration phase of simulation. Configurations actually consist
of two pieces: the library mapping and the configuration itself. The library mapping is used
at compile time to determine into which libraries the source files are to be compiled. Here
is an example of a simple library map file:
library work ../top.v;
library rtlLib lrm_ex_top.v;
library gateLib lrm_ex_adder.vg;
library aLib lrm_ex_adder.v;
Here is an example of a library map file that uses -incdir:
library lib1 src_dir/*.v -incdir ../include_dir2, ../, my_incdir;
The name of the library map file is arbitrary. You specify the library map file using the
-libmap argument to the vlog command (CR-358). Alternatively, you can specify the file
name as the first item on the vlog command line, and the compiler will read it as a library
map file.
The library map file must be compiled along with the Verilog source files. Multiple map
files are allowed but each must be preceded by the -libmap argument.
The library map file and the configuration can exist in the same or different files. If they
are separate, only the map file needs the -libmap argument. The configuration is treated as
any other Verilog source file.
Configurations and the library named “work”
The library named “work” is treated specially by ModelSim (see "The library named
"work"" (UM-58) for details) for Verilog configurations. Consider the following code
example:
config cfg;
design top;
instance top.u1 use work.u1;
endconfig
In this case, work.u1 indicates to load u1 from the current library.