ModelSim SE User's Manual - Electrical and Computer Engineering

UM-234 8 - WLF files (datasets) and virtuals
Virtual functions
ModelSim SE User’s Manual
order to reconstruct the original RTL hierarchy when simulating and driving a
post-synthesis, gate-level implementation.
A virtual signal can be used to reconstruct RTL-level design buses that were broken down
during synthesis. The virtual hide command (CR-342) can be used to hide the display of the
broken-down bits if you don't want them cluttering up the Objects pane.
If the virtual signal has elements from more than one WLF file, it will be automatically
installed in the virtual region virtuals:/Signals.
Virtual signals are not hierarchical – if two virtual signals are concatenated to become a
third virtual signal, the resulting virtual signal will be a concatenation of all the scalar
elements of the first two virtual signals.
The definitions of virtuals can be saved to a macro file using the virtual save command
(CR-349). By default, when quitting, ModelSim will append any newly-created virtuals (that
have not been saved) to the virtuals.do file in the local directory.
If you have virtual signals displayed in the Wave or List window when you save the Wave
or List format, you will need to execute the virtuals.do file (or some other equivalent) to
restore the virtual signal definitions before you re-load the Wave or List format during a
later run. There is one exception: "implicit virtuals" are automatically saved with the Wave
or List format.
Implicit and explicit virtuals
An implicit virtual is a virtual signal that was automatically created by ModelSim without
your knowledge and without you providing a name for it. An example would be if you
expand a bus in the Wave window, then drag one bit out of the bus to display it separately.
That action creates a one-bit virtual signal whose definition is stored in a special location,
and is not visible in the Objects pane or to the normal virtual commands.
All other virtual signals are considered "explicit virtuals".
Virtual functions behave in the GUI like signals but are not aliases of combinations or
elements of signals logged by the kernel. They consist of logical operations on logged
signals and can be dependent on simulation time. They can be displayed in the Objects,
Wave, and List windows and accessed by the examine command (CR-162), but cannot be
set by the force command (CR-180).
Examples of virtual functions include the following:
a function defined as the inverse of a given signal
a function defined as the exclusive-OR of two signals
a function defined as a repetitive clock
a function defined as "the rising edge of CLK delayed by 1.34 ns"
Virtual functions can also be used to convert signal types and map signal values.
The result type of a virtual signal can be any of the types supported in the GUI expression
syntax: integer, real, boolean, std_logic, std_logic_vector, and arrays and records of these
types. Verilog types are converted to VHDL 9-state std_logic equivalents and Verilog net
strengths are ignored.