ModelSim SE User's Manual - Electrical and Computer Engineering

UM-72 4 - VHDL simulation
ModelSim SE User’s Manual
Util package . . . . . . . . . . . . . . . . UM-96
get_resolution . . . . . . . . . . . . . . . UM-96
init_signal_driver() . . . . . . . . . . . . . UM-97
init_signal_spy() . . . . . . . . . . . . . . UM-97
signal_force() . . . . . . . . . . . . . . . UM-97
signal_release() . . . . . . . . . . . . . . UM-97
to_real() . . . . . . . . . . . . . . . . UM-98
to_time() . . . . . . . . . . . . . . . . UM-99
Foreign language interface. . . . . . . . . . . . UM-100
Modeling memory . . . . . . . . . . . . . . UM-101
’87 and ’93 example . . . . . . . . . . . . UM-101
’02 example . . . . . . . . . . . . . . UM-104
Affecting performance by cancelling scheduled events . . . . UM-108
Converting an integer into a bit_vector . . . . . . . . UM-109
This chapter provides an overview of compilation and simulation for VHDL; using the
TextIO package with ModelSim; ModelSim’s implementation of the VITAL (VHDL
Initiative Towards ASIC Libraries) specification for ASIC modeling; and documentation
on ModelSim’s special built-in utilities package.
The TextIO package is defined within the VHDL Language Reference Manual, IEEE Std
1076; it allows human-readable text input from a declared source within a VHDL file
during simulation.
Note: ModelSim VHDL is not supported in ModelSim LE.