ModelSim SE User's Manual - Electrical and Computer Engineering

UM-82 4 - VHDL simulation
Simulating with an elaboration file
Overview
Elaboration file flow
ModelSim SE User’s Manual
The ModelSim compiler generates a library format that is compatible across platforms.
This means the simulator can load your design on any supported platform without having
to recompile first. Though this architecture offers a benefit, it also comes with a possible
detriment: the simulator has to generate platform-specific code every time you load your
design. This impacts the speed with which the design is loaded.
Starting with ModelSim version 5.6, you can generate a loadable image (elaboration file)
which can be simulated repeatedly. On subsequent simulations, you load the elaboration
file rather than loading the design "from scratch." Elaboration files load quickly.
Why an elaboration file?
In many cases design loading time is not that important. For example, if you’re doing
"iterative design," where you simulate the design, modify the source, recompile and
resimulate, the load time is just a small part of the overall flow. However, if your design is
locked down and only the test vectors are modified between runs, loading time may
materially impact overall simulation time, particularly for large designs loading SDF files.
Another reason to use elaboration files is for benchmarking purposes. Other simulator
vendors use elaboration files, and they distinguish between elaboration and run times. If
you are benchmarking ModelSim against another simulator that uses elaboration, make
sure you use an elaboration file with ModelSim as well so you’re comparing like to like.
One caveat with elaboration files is that they must be created and used in the same
environment. The same environment means the same hardware platform, the same OS and
patch version, and the same version of any PLI/FLI code loaded in the simulation.
We recommend the following flow to maximize the benefit of simulating elaboration files.
1 If timing for your design is fixed, include all timing data when you create the elaboration
file (using the -sdf instance= argument). If your timing is not fixed
in a Verilog design, you’ll have to use $sdf_annotate system tasks. Note that use of
$sdf_annotate causes timing to be applied after elaboration.
2 Apply all normal vsim arguments when you create the elaboration file. Some arguments
(primarily related to stimulus) may be superseded later during loading of the elaboration
file (see "Modifying stimulus" (UM-84) below).
3 Load the elaboration file along with any arguments that modify the stimulus (see below).