ModelSim SE User's Manual - Electrical and Computer Engineering

The generic type is determined by the parameter's initial value as follows:
Parameter value Generic type
integer integer
real real
string literal string
The default value of the generic is the same as the parameter's initial value.
Examples
Verilog parameter VHDL generic
parameter p1 = 1 - 3; p1 : integer := -2;
parameter p2 = 3.0; p2 : real := 3.000000;
parameter p3 = "Hello"; p3 : string := "Hello";
VHDL: instantiating Verilog UM-205
Port clause
A port clause is generated if the module has ports. A corresponding VHDL port is defined
for each named Verilog port.
You can set the VHDL port type to bit, std_logic, or vl_logic. If the Verilog port has a
range, then the VHDL port type is bit_vector, std_logic_vector, or vl_logic_vector. If the
range does not depend on parameters, then the vector type will be constrained accordingly,
otherwise it will be unconstrained.
Examples
Verilog port VHDL port
input p1; p1 : in std_logic;
output [7:0] p2; p2 : out std_logic_vector(7 downto 0);
output [4:7] p3; p3 : out std_logic_vector(4 to 7);
inout [width-1:0] p4; p4 : inout std_logic_vector;
Configuration declarations are allowed to reference Verilog modules in the entity aspects
of component configurations. However, the configuration declaration cannot extend into a
Verilog instance to configure the instantiations within the Verilog module.
ModelSim SE User’s Manual