ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-324 12 - Profiling performance and memory use Viewing profiler results The Ranked View Click here to hide or display columns ModelSim SE User’s Manual The profiler provides three views of the collected data – Ranked, Call Tree and Structural. All three views are enabled by selecting View > Profile > View or by typing view profile at the VSIM prompt. This opens the Profile pane. The Profile pane includes selection tabs for the Ranked, Call Tree and Structural views. The Ranked view displays the results of the statistical performance profiler and the memory allocation profiler for each function or instance. By default, ranked profiler results are sorted by values in the In% column, which shows the percentage of the total samples collected for each function or instance. You can sort ranked results by any other column by simply clicking the column heading. Click the down arrow to the left of the Name column to open a Configure Columns dialog, which allows you to select which columns are to be hidden or displayed. The use of colors in the display provides an immediate visual indication of where your design is spending most of its simulation time. By default, red text indicates functions or instances that are consuming 5% or more of simulation time. The Ranked view does not provide hierarchical, function-call information.
The Call Tree view Viewing profiler results UM-325 By default, profiler results in the Call Tree view are sorted according to the Under(%) column, which shows the percentage of the total samples collected for each function or instance and all supporting routines or instances. Sort results by any other column by clicking the column heading. As in the Ranked view, red object names indicate functions or instances that, by default, are consuming 5% or more of simulation time. The Call Tree view differs from the Ranked view in two important respects. Entries in the Name column of the Call Tr ee view are indented in hierarchical order to indicate which functions or routines call which others. A %Parent column in the Call Tree view allows you to see what percentage of a parent routine’s simulation time is used in which subroutines. The Call Tree view presents data in a call-stack format that provides more context than does the ranked view about where simulation time is spent. For example, your models may contain several instances of a utility function that computes the maximum of 3-delay values. A Ranked view might reveal that the simulation spent 60% of its time in this utility function, but would not tell you which routine or routines were making the most use of it. The Call Tree view will reveal which line is calling the function most frequently. Using this information, you might decide that instead of calling the function every time to compute the maximum of the 3-delays, this spot in your VHDL code can be used to compute it just once. You can then store the maximum delay value in a local variable. The two %Parent columns in the Call Tree view show the percent of simulation time or allocated memory a given function or instance is using of its parent’s total simulation time or available memory. From these columns, you can calculate the percentage of total simulation time or memory taken up by any function. For example, if a particular parent entry used 10% of the total simulation time or allocated memory, and it called a routine that used 80% of its simulation time or memory, then the percentage of total simulation time spent in, or memory allocated to, that routine would be 80% of 10%, or 8%. In addition to these differences, the Ranked view displays any particular function only once, regardless of where it was used. In the Call Tree view, the function can appear multiple times – each time in the context of where it was used. ModelSim SE User’s Manual
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ModelSim® Advanced Verification an
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Table of Contents 1 - Introduction
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Delta delays . . . . . . . . . . .
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ModelSim Verilog system tasks and f
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VHDL: instantiating SystemC . . . .
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Creating waveforms from patterns .
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14 - PSL Assertions (UM-359) What a
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17 - Signal Spy (UM-417) Introducti
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Starting the debugger . . . . . . .
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Steps in flow . . . . . . . . . . .
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1 - Introduction Chapter contents M
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ModelSim simulation task overview M
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Basic steps for simulation UM-25 Li
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ModelSim modes of operation ModelSi
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ModelSim graphic interface overview
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Sections in this document Sections
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Sections in this document UM-33 H -
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Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
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Specifying file properties and proj
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Accessing projects from the command
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3 - Design libraries Chapter conten
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Archives Design library overview UM
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Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
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Importing FPGA libraries Importing
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4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
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Reading and writing hexadecimal num
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VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
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BEGIN FOR i IN 0 TO 1023 LOOP we
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Converting an integer into a bit_ve
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5 - Verilog simulation Chapter cont
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Introduction ModelSim Verilog basic
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Incremental compilation Compiling V
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Library usage Compiling Verilog fil
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Verilog-XL compatible compiler argu
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Compiling Verilog files UM-121 The
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Verilog generate statements Compili
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Naming the optimized design Optimiz
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Optimizing Verilog designs UM-127 I
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Simulating Verilog designs Simulato
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`timescale, -t, and rounding Simula
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Simulating Verilog designs UM-133 T
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Simulating Verilog designs UM-135 M
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+pulse_e_style_onevent +pulse_int_e
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Distributed delay mode In distribut
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System tasks and functions UM-147 a
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File I/O tasks $fclose $fopen $fwri
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System tasks and functions UM-151 T
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Compiler directives Compiler direct
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ModelSim compiler directives The fo
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Determining which memories were imp
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6 - SystemC simulation Chapter cont
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Supported platforms and compiler ve
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Usage flow for SystemC-only designs
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Code modification examples Compilin
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Example 3 Compiling SystemC files U
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Restrictions on compiling with HP a
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Issues with C++ templates Templatiz
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Simulating SystemC designs Loading
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Initialization and cleanup of Syste
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Waveform compare Debugging the desi
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Debugging the design UM-179 The gdb
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Viewing FIFOs SystemC object and ty
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OSCI 2.1 features supported Differe
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Troubleshooting SystemC errors UM-1
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7 - Mixed-language simulation Chapt
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Usage flow for mixed-language simul
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Simulator resolution limit Runtime
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Mapping data types Verilog to VHDL
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VHDL to Verilog mappings Mapping da
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Channels Ports Verilog mapping sc_b
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Verilog sc_logic sc_bit bool SuX 'X
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SystemC VHDL sc_int, sc_uint bit_ve
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VHDL: instantiating Verilog Verilog
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The generic type is determined by t
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Verilog: instantiating VHDL VHDL in
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SystemC: instantiating Verilog Veri
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Example #2 SystemC: instantiating V
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}; } #endif // Connect ports chip->
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Example of parameter use format_cha
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SystemC: instantiating VHDL VHDL in
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Example SystemC: instantiating VHDL
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); END ringbuf; ARCHITECTURE RTL OF
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vgencomp component declaration vgen
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8 - WLF files (datasets) and virtua
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Saving a simulation to a WLF file O
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Managing multiple datasets WLF file
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Saving at intervals with Dataset Sn
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Virtual Objects (User-defined buses
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Virtual regions Virtual types Virtu
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9 - Waveform analysis Chapter conte
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Introduction Objects you can view W
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Wave window overview UM-241 Here is
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List window overview List window ov
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Measuring time with cursors in the
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Jumping to a signal transition Meas
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Zooming the Wave window display Zoo
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Searching in the Wave and List wind
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Using the Expression Builder for ex
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Formatting the Wave window Setting
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Formatting the Wave window UM-257 3
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Formatting the List window Setting
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Saving the window format Saving the
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Saving List window data to a file S
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Configuring new line triggering in
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Configuring new line triggering in
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Miscellaneous tasks Examining wavef
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Comparison Wizard Waveform Compare
Page 273 and 274: Test Dataset Waveform Compare UM-27
Page 275 and 276: Adding regions Waveform Compare UM-
Page 277 and 278: Clocked comparison Waveform Compare
Page 279 and 280: Viewing differences in the Wave win
Page 281 and 282: Compare icons Waveform Compare UM-2
Page 283 and 284: Comparing hierarchical and flattene
Page 285 and 286: 10 - Generating stimulus with Wavef
Page 287 and 288: Getting started You can use Wavefor
Page 289 and 290: Creating waveforms from patterns Cr
Page 291 and 292: Editing waveforms GR-291 These comm
Page 293 and 294: Simulating directly from waveform e
Page 295 and 296: Driving simulation with the saved s
Page 297 and 298: Saving the waveform editor commands
Page 299 and 300: 11 - Tracing signals with the Dataf
Page 301 and 302: Adding objects to the window Adding
Page 303 and 304: Exploring the connectivity of your
Page 305 and 306: Zooming and panning Zooming with to
Page 307 and 308: Tracing the source of an unknown (X
Page 309 and 310: Finding objects by name in the Data
Page 311 and 312: Printing on Windows platforms Selec
Page 313 and 314: Symbol mapping Symbol mapping UM-31
Page 315 and 316: Configuring window options Configur
Page 317 and 318: 12 - Profiling performance and memo
Page 319 and 320: Getting started Memory allocation p
Page 321 and 322: Enabling the statistical sampling p
Page 323: Interpreting profiler data Interpre
Page 327 and 328: Viewing profile details Viewing pro
Page 329 and 330: Integration with Source windows Int
Page 331 and 332: Reporting profiler results Reportin
Page 333 and 334: 13 - Measuring code coverage Chapte
Page 335 and 336: Supported types ModelSim code cover
Page 337 and 338: Enabling code coverage Enabling cod
Page 339 and 340: Enabling code coverage UM-339 Next,
Page 341 and 342: Viewing coverage data in the Source
Page 343 and 344: Toggle coverage Enabling Toggle cov
Page 345 and 346: 3 Produce the report with the toggl
Page 347 and 348: Excluding objects from coverage Exc
Page 349 and 350: end instance Default filter file Ex
Page 351 and 352: XML output Reporting coverage data
Page 353 and 354: Instance report with line details R
Page 355 and 356: Coverage statistics details Conditi
Page 357 and 358: Coverage statistics details UM-357
Page 359 and 360: 14 - PSL Assertions Chapter content
Page 361 and 362: PSL assertion language What are ass
Page 363 and 364: Using cover directives Using assert
Page 365 and 366: REF2); signal mem_state : memory_st
Page 367 and 368: } // Check the write cycle property
Page 369 and 370: Multi-clocked properties and defaul
Page 371 and 372: Using endpoints in HDL code Example
Page 373 and 374: Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
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Mistaking a component or module nam
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19 - Value Change Dump (VCD) Files
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Checkpoint/restore and writing VCD
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Example 3 — Mixed-HDL design Firs
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ModelSim VCD commands and VCD tasks
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A VCD file from source to output VH
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x) x* x+ x, $end #300 $dumpon 1! 0"
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Capturing port driver data Supporte
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Example VCD output from vcd dumppor
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20 - Tcl and macros (DO files) Chap
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Tcl commands Tcl commands UM-473 Fo
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Tcl command syntax UM-475 7 If a wo
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set command syntax Tcl command synt
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Variable substitution System comman
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ModelSim Tcl time commands Conversi
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Tcl examples This is an example of
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} if {$windowName == ""} { # Dialog
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Macros (DO files) Creating DO files
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set vFilesExist 1 } shift } if {$vh
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Using the Tcl source command with D
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The Tcl Debugger Starting the debug
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Breakpoints The Tcl Debugger UM-495
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TclPro Debugger TclPro Debugger UM-
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A - ModelSim GUI changes Appendix c
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Main window changes UM-501 See "Cus
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Main window changes UM-503 File > O
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View menu The View menu has been re
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Tools menu The 6.0 Main window Tool
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List window changes File menu The L
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File menu See "Memory windows" (GR-
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View menu The Memory window > View
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Edit menu The Signals window > Edit
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View menu The Source window > File
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B - ModelSim variables Appendix con
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Environment variables Environment v
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Library mapping with environment va
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[Library] library path variables Va
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[vcom] VHDL compiler control variab
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[vsim] simulator control variables
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Preference variables located in INI
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Commonly used INI variables Prefere
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Force command defaults Preference v
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Variable precedence Variable preced
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Special considerations for the now
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C - Error and warning messages Appe
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ModelSim message system UM-547 Ther
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Exit codes The table below describe
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Miscellaneous messages Miscellaneou
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Miscellaneous messages UM-553 model
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VSIM license lost Message text Cons
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Suggested action Multiply defined s
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D - Verilog PLI / VPI / DPI Chapter
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Registering PLI applications Regist
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Registering VPI applications Exampl
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Registering DPI applications Regist
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For Windows only: Run a preliminary
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32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
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E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
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Environment variables accessed duri
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Initialization sequence Initializat
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G - Logic Modeling SmartModels Appe
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Creating foreign architectures with
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Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
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H - Logic Modeling hardware models
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Creating foreign architectures with
Page 631 and 632:
Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
Page 637 and 638:
Graphics shall only use or disclose
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Index CR = Command Reference, UM =
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Stop on quit mode UM-414 C Debug se
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mem search CR-204 modelsim CR-206 n
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ange checking in VHDL CR-316, UM-74
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Add Folder GR-47 C Debug setup GR-9
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F -f CR-360 F8 function key UM-607
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Verilog modules UM-125 VHDL subprog
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Memory window GR-169 GUI changes UM
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optimizing Verilog designs design o
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eaders and drivers UM-303 readers c
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adix specifying for examine CR-163
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system tasks VCD UM-461 Verilog UM-
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U -u CR-365 unbound component GR-53
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library clause UM-64 mixed designs
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text editing UM-605 windows Active
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