ModelSim SE User's Manual - Electrical and Computer Engineering

UM-220 7 - Mixed-language simulation
ModelSim SE User’s Manual
};
#endif
// VHDL module instance
ringbuf* chip;
SC_CTOR(test_ringbuf)
: iclock("iclock"),
...
...
{
const char* generic_list[9];
generic_list[0] = strdup("int_param=4");
generic_list[1] = strdup("real_param=2.6");
generic_list[2] = strdup("str_param=\"Hello\"");
generic_list[3] = strdup("bool_param=false");
generic_list[4] = strdup("char_param=Y");
generic_list[5] = strdup("bit_param=0");
generic_list[6] = strdup("bv_param=010");
generic_list[7] = strdup("logic_param=Z");
generic_list[8] = strdup("lv_param=01XZ");
// Cleanup the memory allocated for the generic list
for (int = 0; i < 9; i++;)
free((char*)generic_list[i]);
// Create VHDL module instance.
chip = new ringbuf("chip", "ringbuf", 9, generic_list);
---------------------------------------------------------------------------
-- test_ringbuf.cpp
#include "test_ringbuf.h"
SC_MODULE_EXPORT(test_ringbuf);
---------------------------------------------------------------------------
-- ringbuf.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE std.textio.all;
ENTITY ringbuf IS
generic (
int_param : integer;
real_param : real;
str_param : string;
bool_param : boolean;
char_param : character;
bit_param : bit;
bv_param : bit_vector(0 to 2);
logic_param : std_logic;
lv_param : std_logic_vector(3 downto 0));
PORT (
clock : IN std_logic;
..
...