ModelSim SE User's Manual - Electrical and Computer Engineering

A VCD file from source to output
VHDL source code
VCD simulator commands
A VCD file from source to output UM-463
The following example shows the VHDL source, a set of simulator commands, and the
resulting VCD output.
The design is a simple shifter device represented by the following VHDL source code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SHIFTER_MOD is
port (CLK, RESET, data_in : IN STD_LOGIC;
Q : INOUT STD_LOGIC_VECTOR(8 downto 0));
END SHIFTER_MOD ;
architecture RTL of SHIFTER_MOD is
begin
process (CLK,RESET)
begin
if (RESET = '1') then
Q '0') ;
elsif (CLK'event and CLK = '1') then
Q