ModelSim SE User's Manual - Electrical and Computer Engineering

Example
`timescale 1 ps / 1 ps
module testbench;
reg clk0;
initial begin
clk0 = 1;
forever begin
#20 clk0 = ~clk0;
end
end
initial begin
$init_signal_driver("clk0", "/testbench/uut/blk1/clk", , , 1);
$init_signal_driver("clk0", "/testbench/uut/blk2/clk", 100, 1);
end
...
endmodule
$init_signal_driver UM-431
The above example creates a local clock (clk0) and connects it to two clocks within the
design hierarchy. The .../blk1/clk will match local clk0 and a message will be displayed.
The .../blk2/clk will match the local clk0 but be delayed by 100 ps. For the second call to
work, the .../blk2/clk must be a VHDL based signal, because if it were a Verilog net a 100
ps inertial delay would consume the 40 ps clock period. Verilog nets are limited to only
inertial delays and thus the setting of 1 (transport delay) would be ignored.
ModelSim SE User’s Manual