ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-158 5 - Verilog simulation Verilog PLI/VPI and SystemVerilog DPI ModelSim SE User’s Manual ModelSim supports the use of the Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) and the SystemVerilog DPI (Direct Programming Interface). These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface. For more information on the ModelSim implementation, see Appendix D - Verilog PLI / VPI / DPI.
6 - SystemC simulation Chapter contents Introduction . . . . . . . . . . . . . . . UM-160 Supported platforms and compiler versions . . . . . . . UM-161 Building gcc with custom configuration options . . . . . UM-161 HP Limitations for SystemC . . . . . . . . . . UM-162 Usage flow for SystemC-only designs . . . . . . . . . UM-163 Compiling SystemC files . . . . . . . . . . . . UM-164 Creating a design library . . . . . . . . . . . UM-164 Modifying SystemC source code . . . . . . . . . UM-164 Invoking the SystemC compiler . . . . . . . . . UM-167 Compiling optimized and/or debug code . . . . . . . UM-167 Specifying an alternate g++ installation . . . . . . . UM-168 Maintaining portability between OSCI and ModelSim . . . UM-168 Restrictions on compiling with HP aCC . . . . . . . UM-169 Switching platforms and compilation . . . . . . . . UM-169 Using sccom vs. raw C++ compiler . . . . . . . . UM-170 Linking the compiled source . . . . . . . . . . . UM-164 sccom -link . . . . . . . . . . . . . . UM-172 Simulating SystemC designs . . . . . . . . . . . UM-173 Running simulation . . . . . . . . . . . . UM-173 Debugging the design . . . . . . . . . . . . . UM-176 Viewable SystemC objects . . . . . . . . . . UM-176 Source-level debug . . . . . . . . . . . . UM-178 SystemC object and type display in ModelSim . . . . . . UM-176 Support for aggregates . . . . . . . . . . . UM-180 Viewing FIFOs . . . . . . . . . . . . . UM-181 Differences between ModelSim and the OSCI simulator . . . . UM-182 Fixed point types . . . . . . . . . . . . . UM-182 OSCI 2.1 features supported . . . . . . . . . . UM-183 Troubleshooting SystemC errors . . . . . . . . . . UM-184 Errors during loading . . . . . . . . . . . . UM-184 Note: The functionality described in this chapter requires a systemc license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature. UM-159 ModelSim SE User’s Manual
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ModelSim® Advanced Verification an
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Table of Contents 1 - Introduction
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Delta delays . . . . . . . . . . .
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ModelSim Verilog system tasks and f
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VHDL: instantiating SystemC . . . .
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Creating waveforms from patterns .
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14 - PSL Assertions (UM-359) What a
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17 - Signal Spy (UM-417) Introducti
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Starting the debugger . . . . . . .
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Steps in flow . . . . . . . . . . .
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1 - Introduction Chapter contents M
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ModelSim simulation task overview M
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Basic steps for simulation UM-25 Li
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ModelSim modes of operation ModelSi
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ModelSim graphic interface overview
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Sections in this document Sections
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Sections in this document UM-33 H -
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Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
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Specifying file properties and proj
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Accessing projects from the command
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3 - Design libraries Chapter conten
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Archives Design library overview UM
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Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
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Importing FPGA libraries Importing
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4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
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Reading and writing hexadecimal num
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VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
Page 107 and 108: BEGIN FOR i IN 0 TO 1023 LOOP we
Page 109 and 110: Converting an integer into a bit_ve
Page 111 and 112: 5 - Verilog simulation Chapter cont
Page 113 and 114: Introduction ModelSim Verilog basic
Page 115 and 116: Incremental compilation Compiling V
Page 117 and 118: Library usage Compiling Verilog fil
Page 119 and 120: Verilog-XL compatible compiler argu
Page 121 and 122: Compiling Verilog files UM-121 The
Page 123 and 124: Verilog generate statements Compili
Page 125 and 126: Naming the optimized design Optimiz
Page 127 and 128: Optimizing Verilog designs UM-127 I
Page 129 and 130: Simulating Verilog designs Simulato
Page 131 and 132: `timescale, -t, and rounding Simula
Page 133 and 134: Simulating Verilog designs UM-133 T
Page 135 and 136: Simulating Verilog designs UM-135 M
Page 137 and 138: +pulse_e_style_onevent +pulse_int_e
Page 139 and 140: Creating an elaboration file Loadin
Page 141 and 142: Example Simulating with an elaborat
Page 143 and 144: Controlling checkpoint file compres
Page 145 and 146: Distributed delay mode In distribut
Page 147 and 148: System tasks and functions UM-147 a
Page 149 and 150: File I/O tasks $fclose $fopen $fwri
Page 151 and 152: System tasks and functions UM-151 T
Page 153 and 154: Compiler directives Compiler direct
Page 155 and 156: ModelSim compiler directives The fo
Page 157: Determining which memories were imp
Page 161 and 162: Supported platforms and compiler ve
Page 163 and 164: Usage flow for SystemC-only designs
Page 165 and 166: Code modification examples Compilin
Page 167 and 168: Example 3 Compiling SystemC files U
Page 169 and 170: Restrictions on compiling with HP a
Page 171 and 172: Issues with C++ templates Templatiz
Page 173 and 174: Simulating SystemC designs Loading
Page 175 and 176: Initialization and cleanup of Syste
Page 177 and 178: Waveform compare Debugging the desi
Page 179 and 180: Debugging the design UM-179 The gdb
Page 181 and 182: Viewing FIFOs SystemC object and ty
Page 183 and 184: OSCI 2.1 features supported Differe
Page 185 and 186: Troubleshooting SystemC errors UM-1
Page 187 and 188: 7 - Mixed-language simulation Chapt
Page 189 and 190: Usage flow for mixed-language simul
Page 191 and 192: Simulator resolution limit Runtime
Page 193 and 194: Mapping data types Verilog to VHDL
Page 195 and 196: VHDL to Verilog mappings Mapping da
Page 197 and 198: Channels Ports Verilog mapping sc_b
Page 199 and 200: Verilog sc_logic sc_bit bool SuX 'X
Page 201 and 202: SystemC VHDL sc_int, sc_uint bit_ve
Page 203 and 204: VHDL: instantiating Verilog Verilog
Page 205 and 206: The generic type is determined by t
Page 207 and 208: Verilog: instantiating VHDL VHDL in
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SystemC: instantiating Verilog Veri
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Example #2 SystemC: instantiating V
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}; } #endif // Connect ports chip->
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Example of parameter use format_cha
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SystemC: instantiating VHDL VHDL in
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Example SystemC: instantiating VHDL
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); END ringbuf; ARCHITECTURE RTL OF
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vgencomp component declaration vgen
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8 - WLF files (datasets) and virtua
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Saving a simulation to a WLF file O
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Managing multiple datasets WLF file
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Saving at intervals with Dataset Sn
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Virtual Objects (User-defined buses
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Virtual regions Virtual types Virtu
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9 - Waveform analysis Chapter conte
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Introduction Objects you can view W
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Wave window overview UM-241 Here is
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List window overview List window ov
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Measuring time with cursors in the
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Jumping to a signal transition Meas
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Zooming the Wave window display Zoo
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Searching in the Wave and List wind
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Using the Expression Builder for ex
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Formatting the Wave window Setting
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Formatting the Wave window UM-257 3
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Formatting the List window Setting
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Saving the window format Saving the
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Saving List window data to a file S
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Configuring new line triggering in
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Configuring new line triggering in
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Miscellaneous tasks Examining wavef
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Comparison Wizard Waveform Compare
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Test Dataset Waveform Compare UM-27
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Adding regions Waveform Compare UM-
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Clocked comparison Waveform Compare
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Viewing differences in the Wave win
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Compare icons Waveform Compare UM-2
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Comparing hierarchical and flattene
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10 - Generating stimulus with Wavef
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Getting started You can use Wavefor
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Creating waveforms from patterns Cr
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Editing waveforms GR-291 These comm
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Simulating directly from waveform e
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Driving simulation with the saved s
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Saving the waveform editor commands
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11 - Tracing signals with the Dataf
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Adding objects to the window Adding
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Exploring the connectivity of your
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Zooming and panning Zooming with to
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Tracing the source of an unknown (X
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Finding objects by name in the Data
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Printing on Windows platforms Selec
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Symbol mapping Symbol mapping UM-31
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Configuring window options Configur
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12 - Profiling performance and memo
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Getting started Memory allocation p
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Enabling the statistical sampling p
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Interpreting profiler data Interpre
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The Call Tree view Viewing profiler
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Viewing profile details Viewing pro
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Integration with Source windows Int
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Reporting profiler results Reportin
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13 - Measuring code coverage Chapte
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Supported types ModelSim code cover
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Enabling code coverage Enabling cod
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Enabling code coverage UM-339 Next,
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Viewing coverage data in the Source
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Toggle coverage Enabling Toggle cov
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3 Produce the report with the toggl
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Excluding objects from coverage Exc
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end instance Default filter file Ex
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XML output Reporting coverage data
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Instance report with line details R
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Coverage statistics details Conditi
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Coverage statistics details UM-357
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14 - PSL Assertions Chapter content
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PSL assertion language What are ass
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Using cover directives Using assert
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REF2); signal mem_state : memory_st
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} // Check the write cycle property
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Multi-clocked properties and defaul
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Using endpoints in HDL code Example
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Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
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Mistaking a component or module nam
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19 - Value Change Dump (VCD) Files
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Checkpoint/restore and writing VCD
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Example 3 — Mixed-HDL design Firs
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ModelSim VCD commands and VCD tasks
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A VCD file from source to output VH
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x) x* x+ x, $end #300 $dumpon 1! 0"
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Capturing port driver data Supporte
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Example VCD output from vcd dumppor
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20 - Tcl and macros (DO files) Chap
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Tcl commands Tcl commands UM-473 Fo
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Tcl command syntax UM-475 7 If a wo
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set command syntax Tcl command synt
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Variable substitution System comman
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ModelSim Tcl time commands Conversi
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Tcl examples This is an example of
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} if {$windowName == ""} { # Dialog
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Macros (DO files) Creating DO files
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set vFilesExist 1 } shift } if {$vh
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Using the Tcl source command with D
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The Tcl Debugger Starting the debug
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Breakpoints The Tcl Debugger UM-495
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TclPro Debugger TclPro Debugger UM-
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A - ModelSim GUI changes Appendix c
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Main window changes UM-501 See "Cus
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Main window changes UM-503 File > O
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View menu The View menu has been re
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Tools menu The 6.0 Main window Tool
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List window changes File menu The L
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File menu See "Memory windows" (GR-
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View menu The Memory window > View
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Edit menu The Signals window > Edit
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View menu The Source window > File
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B - ModelSim variables Appendix con
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Environment variables Environment v
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Library mapping with environment va
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[Library] library path variables Va
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[vcom] VHDL compiler control variab
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[vsim] simulator control variables
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Preference variables located in INI
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Commonly used INI variables Prefere
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Force command defaults Preference v
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Variable precedence Variable preced
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Special considerations for the now
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C - Error and warning messages Appe
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ModelSim message system UM-547 Ther
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Exit codes The table below describe
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Miscellaneous messages Miscellaneou
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Miscellaneous messages UM-553 model
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VSIM license lost Message text Cons
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Suggested action Multiply defined s
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D - Verilog PLI / VPI / DPI Chapter
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Registering PLI applications Regist
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Registering VPI applications Exampl
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Registering DPI applications Regist
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For Windows only: Run a preliminary
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32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
Page 603 and 604:
E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
Page 613 and 614:
Environment variables accessed duri
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Initialization sequence Initializat
Page 617 and 618:
G - Logic Modeling SmartModels Appe
Page 619 and 620:
Creating foreign architectures with
Page 621 and 622:
Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
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H - Logic Modeling hardware models
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Creating foreign architectures with
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Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
Page 637 and 638:
Graphics shall only use or disclose
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Index CR = Command Reference, UM =
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Stop on quit mode UM-414 C Debug se
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mem search CR-204 modelsim CR-206 n
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ange checking in VHDL CR-316, UM-74
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Add Folder GR-47 C Debug setup GR-9
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F -f CR-360 F8 function key UM-607
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Verilog modules UM-125 VHDL subprog
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Memory window GR-169 GUI changes UM
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optimizing Verilog designs design o
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eaders and drivers UM-303 readers c
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adix specifying for examine CR-163
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system tasks VCD UM-461 Verilog UM-
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U -u CR-365 unbound component GR-53
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library clause UM-64 mixed designs
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text editing UM-605 windows Active
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