ModelSim SE User's Manual - Electrical and Computer Engineering

Library usage
Compiling Verilog files UM-117
All modules and UDPs in a Verilog design must be compiled into one or more libraries.
One library is usually sufficient for a simple design, but you may want to organize your
modules into various libraries for a complex design. If your design uses different modules
having the same name, then you are required to put those modules in different libraries
because design unit names must be unique within a library.
The following is an example of how you may organize your ASIC cells into one library and
the rest of your design into another:
% vlib work
% vlib asiclib
% vlog -work asiclib and2.v or2.v
-- Compiling module and2
-- Compiling module or2
Top level modules:
and2
or2
% vlog top.v
-- Compiling module top
Top level modules:
top
Note that the first compilation uses the -work asiclib argument to instruct the compiler to
place the results in the asiclib library rather than the default work library.
Library search rules
Since instantiation bindings are not determined at compile time, you must instruct the
simulator to search your libraries when loading the design. The top-level modules are
loaded from the library named work unless you prefix the modules with the .
option. All other Verilog instantiations are resolved in the following order:
Search libraries specified with -Lf arguments in the order they appear on the command
line.
Search the library specified in the "Verilog-XL `uselib compiler directive" (UM-120).
Search libraries specified with -L arguments in the order they appear on the command
line.
Search the work library.
Search the library explicitly named in the special escaped identifier instance name.
ModelSim SE User’s Manual