ModelSim SE User's Manual - Electrical and Computer Engineering

Example #2
SystemC: instantiating Verilog UM-211
Another variation of the SystemC foreign module declaration for the same Verilog module
might be:
class counter : public sc_foreign_module {
public:
...
...
...
counter(sc_module_name nm, char* hdl_name)
: sc_foreign_module(nm, hdl_name),
clock("clock"),
...
...
...
{}
};
The instantiation of this module would be:
counter dut("dut", "lib.counter");
Parameter support for SystemC instantiating Verilog
Since the SystemC language has no concept of parameters, parameterized values must be
passed from a SystemC parent to a Verilog child through the SystemC foreign module
(sc_foreign_module). See "SystemC foreign module declaration" (UM-209) for information
regarding the creation of sc_foreign_module.
Generic parameters in sc_foreign_module constructor
To instantiate a Verilog module containing parameterized values into the SystemC design,
you must pass two parameters to the sc_foreign_module constructor: the number of
parameters (int num_generics), and the parameter list (const char* generic_list). The
generic_list is listed as an array of const char*.
If you create your foreign module manually (see "Guidelines for manual creation" (UM-
210)), you must also pass the parameter information to the sc_foreign_module constructor.
If you use scgenmod to create the foreign module declaration, the parameter information
is detected in the HDL child and is incorporated automatically.
Example
Following the example shown above (UM-211), let’s see the parameter information that
would be passed to the SystemC foreign module declaration:
class counter : public sc_foreign_module {
public:
sc_in clk;
...
counter(sc_midule_name nm, char* hdl_name
int num_generics, const char* generic_list)
: sc_foreign_module(nm, hdl_name, num_generics,
generic_list),
{}
};
ModelSim SE User’s Manual