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ModelSim SE User's Manual - Electrical and Computer Engineering

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Examples<br />

Optional arguments can be omitted by using commas or by leaving them out if they are at<br />

the end of the argument list. For example, to specify only the SDF file <strong>and</strong> the instance to<br />

which it applies:<br />

$sdf_annotate("myasic.sdf", testbench.u1);<br />

To also specify maximum delay values:<br />

SDF to Verilog construct matching<br />

$sdf_annotate("myasic.sdf", testbench.u1, , , "maximum");<br />

The annotator matches SDF constructs to corresponding Verilog constructs in the cells.<br />

Usually, the cells contain path delays <strong>and</strong> timing checks within specify blocks. For each<br />

SDF construct, the annotator locates the cell instance <strong>and</strong> updates each specify path delay<br />

or timing check that matches. An SDF construct can have multiple matches, in which case<br />

each matching specify statement is updated with the SDF timing value. SDF constructs are<br />

matched to Verilog constructs as follows:<br />

IOPATH is matched to specify path delays or primitives:<br />

SDF Verilog<br />

(IOPATH (posedge clk) q (3) (4)) (posedge clk => q) = 0;<br />

(IOPATH a y (3) (4)) buf u1 (y, a);<br />

The IOPATH construct usually annotates path delays. If <strong>ModelSim</strong> can’t locate a<br />

corresponding specify path delay, it returns an error unless you use the<br />

+sdf_iopath_to_prim_ok argument to vsim (CR-373). If you specify that argument <strong>and</strong> the<br />

module contains no path delays, then all primitives that drive the specified output port are<br />

annotated.<br />

INTERCONNECT <strong>and</strong> PORT are matched to input ports:<br />

SDF Verilog<br />

(INTERCONNECT u1.y u2.a (5)) input a;<br />

(PORT u2.a (5)) inout a;<br />

Both of these constructs identify a module input or inout port <strong>and</strong> create an internal net that<br />

is a delayed version of the port. This is called a Module Input Port Delay (MIPD). All<br />

primitives, specify path delays, <strong>and</strong> specify timing checks connected to the original port are<br />

reconnected to the new MIPD net.<br />

PATHPUL<strong>SE</strong> <strong>and</strong> GLOBALPATHPUL<strong>SE</strong> are matched to specify path delays:<br />

SDF Verilog<br />

(PATHPUL<strong>SE</strong> a y (5) (10)) (a => y) = 0;<br />

(GLOBALPATHPUL<strong>SE</strong> a y (30) (60)) (a => y) = 0;<br />

Verilog SDF UM-445<br />

<strong>ModelSim</strong> <strong>SE</strong> User’s <strong>Manual</strong>

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