ModelSim SE User's Manual - Electrical and Computer Engineering

5 - Verilog simulation
Chapter contents
Introduction . . . . . . . . . . . . . . . UM-113
ModelSim Verilog basic flow . . . . . . . . . . UM-113
Compiling Verilog files . . . . . . . . . . . . UM-114
Incremental compilation . . . . . . . . . . . UM-115
Library usage . . . . . . . . . . . . . . UM-117
Verilog-XL compatible compiler arguments . . . . . . UM-119
Verilog-XL `uselib compiler directive . . . . . . . UM-120
Verilog configurations . . . . . . . . . . . UM-122
Verilog generate statements . . . . . . . . . . UM-123
Optimizing Verilog designs . . . . . . . . . . . UM-124
Running vopt on your design . . . . . . . . . . UM-124
Naming the optimized design . . . . . . . . . . UM-125
Enabling design object visibility with the +acc option . . . UM-126
Optimizing gate-level designs. . . . . . . . . . UM-127
Event order and optimized designs . . . . . . . . UM-128
Timing checks in optimized designs . . . . . . . . UM-128
Simulating Verilog designs . . . . . . . . . . . UM-129
Simulator resolution limit . . . . . . . . . . . UM-129
Event ordering in Verilog designs . . . . . . . . UM-132
Negative timing check limits . . . . . . . . . . UM-136
Verilog-XL compatible simulator arguments . . . . . . UM-136
Simulating with an elaboration file . . . . . . . . . UM-138
Overview . . . . . . . . . . . . . . . UM-138
Elaboration file flow . . . . . . . . . . . . UM-138
Creating an elaboration file . . . . . . . . . . UM-139
Loading an elaboration file . . . . . . . . . . UM-139
Modifying stimulus . . . . . . . . . . . . UM-140
Using with the PLI or FLI. . . . . . . . . . . UM-140
Checkpointing and restoring simulations . . . . . . . . UM-142
Checkpoint file contents . . . . . . . . . . . UM-142
Controlling checkpoint file compression . . . . . . . UM-143
The difference between checkpoint/restore and restart . . . UM-143
Using macros with restart and checkpoint/restore . . . . UM-143
Cell libraries . . . . . . . . . . . . . . . UM-144
SDF timing annotation . . . . . . . . . . . UM-144
Delay modes . . . . . . . . . . . . . . UM-144
System tasks and functions . . . . . . . . . . . UM-146
IEEE Std 1364 system tasks and functions . . . . . . UM-146
Verilog-XL compatible system tasks and functions . . . . UM-150
ModelSim Verilog system tasks and functions . . . . . UM-152
Compiler directives . . . . . . . . . . . . . UM-153
IEEE Std 1364 compiler directives . . . . . . . . UM-153
UM-111
ModelSim SE User’s Manual